What’s New
- Rising to the Verification Challenge of Open Source — Tech Design Forum
- Podcast: DAC 2022 – Digital Twins, Cloud EDA, Intelligent Design — EE Times, 17:05 Dave Kelf Interview
- Breker Verification Systems and Codasip Announce Co-operation to Drive Open, Commercial-Grade RISC-V SoC Verification Processes
- Imperas Announces Partnership with Breker to Drive Rigorous Processor to System Level Verification for RISC-V
- Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies
Featured Video
SystemUVM™ — Empowering the UVM Engineering Team
The 40-minute video introduces you to SystemUVM, a framework designed to simplify specification model composition for test content synthesis with a UVM/SystemVerilog syntactic and semantic approach familiar to universal verification methodology (UVM) engineers. The video demonstrates how Breker’s SystemUVM UVM-style specification model drives test content synthesis, leveraging artificial intelligence (AI) planning algorithms for deep sequential bug hunting in existing UVM environments.
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Upcoming Event
DVCon Europe
December 6-7 | Munich, Germany
Panel: Are processor/SoC discontinuities turning verification on its head?
December 7 | 4:45 – 5:45pm