Arm SoCReady
Arm SoCReady SystemVIP
Off-the-Shelf Arm SoC Verification with Synthesis Amplification
Comprehensive
Comprehensive test suite for all Arm v8/v9 SoC integrity issues, ties in to Coherency and other SystemVIPs
Synthesis backbone
Synthesis backbone drives high coverage, corner case bug hunting, performance profiling, extensibility
Portable
Self-checking content portable across simulation, emulation, and post silicon, with debug & coverage analysis
Arm SoC Verification Challenges
Arm’s processors are verified to a high degree of coverage. However, the SoCs in which they are integrated can vary dramatically. Ensuring that the SoC is “SystemReady” and works infallibly requires more than just register read/write testing and booting the OS. The Arm v8 architecture has been available for many years and is robust. However, the new Arm v9 architecture is less proven, and some integration issues have been noticed.
Arm SoCReady SystemVIP Description
Breker’s Arm SoCReady SystemVIP provides a comprehensive range of unique SoC tests specifically designed to thoroughly evaluate an Arm-based SoC for correct operation. The SystemVIP exercises the core or cores within the context of the SoC, manipulating SoC components to ensure correct functionality. Built on top of Breker’s Test Suite Synthesis, the SystemVIP includes synthesis technologies that amplifies test coverage and corner case detection to find the most obscure of functional and performance bugs.
The SystemVIP is fully portable across a range of execution platforms (simulation, emulation, prototyping, post-silicon and virtual platforms) and can be configured and extended for many architectures. All tests are self-checking, include debug and coverage information, and are coverage-driven to allow upfront selection of required coverage. The SystemVIP comes with an integrated debugger-profiler for system-level analysis and scenario coverage views.
| Random Memory Tests | Test Cores/Fabrics/Memory controllers across memory types |
| Random Register Tests | Read/write test to all uncore registers |
| System Interrupts | Randomized interrupts through CLINT |
| Multicore Execution | For weakly-ordered memory protocols |
| Atomic Operation | Across all memory types |
| System Coherency | Cover all cache transitions, evictions, snoops |
| System Paging/IOMMU | System memory virtualization |
| System Security | Register and memory protection across system |
| Power Management | System-wide sleep/wakeup and voltage/frequency scaling |
| Packet Generation | Generating networking packets for I/O testing |
| Interface Testing | Analyzing coherent interfaces including CXL & UCle |
| SoC Profiling | Layering concurrent tests to check operation under stress |
| Firmware-First | Executing SW on block or subsystem without processor |
Extensive System Integrity Test Suite
A verification suite designed to test the SoCs in which the processor cores operate requires a layered approach. External microarchitectural operation is validated first before moving to integration functionality and execution component performance.
The comprehensive test suite includes a range of load store functional, performance and hazard evaluation, interrupt and exception testing, various memory verification processes, such as memory ordering, atomic instructions, and others. Multicore operation is also evaluated along with coherency and paging testing, as required. Functional bugs are evaluated, as well as issues related to performance bottlenecks and other system integrity problems.
SystemVIP Test Suite Synthesis Amplification
The SystemVIP is built upon Breker’s Test Suite Synthesis platform. The platform allows for a high degree of scenario and functional coverage, together with corner case bug hunting that is far more effective than what is possible with traditional, template-driven test generators. Find out more about test suite synthesis amplification.