SystemVIP Overview
SystemVIP Library Overview
Prepackaged System Verification with Test Suite Synthesis Amplification
Comprehensive
Comprehensive test suite library targeting a broad range of system scenarios
Synthesis backbone
Synthesis backbone drives high coverage, corner case bug hunting, performance profiling, extensibility
Portable
Self-checking content portable across simulation, emulation, and post silicon, with debug & coverage analysis
Breker SystemVIP
Breker provides a library of System Verification Intellectual Property (SystemVIP) that includes prepackaged, self-checking test suites for a range of typical system verification scenarios. These commercial grade test suites are prepackaged, so they can be applied to many designs and immediately provide a full verification environment.
The SystemVIP scenarios are built upon Breker’s test suite synthesis solution, enabling high coverage test generation using AI Planning Algorithms, test cross combination and concurrent test scheduling. This approach far exceeds traditional template-driven test suites by executing extremely unpredictable operational scenarios for comprehensive bug hunting. The tests are fully portable across UVM testbenches, SoC designs with software and hardware driven tests, Post Silicon and C-based Virtual Platforms, running on simulation, emulation, prototyping, and hardware tests. They include performance profiling as well as functional tests, concurrent debug capabilities and scenario coverage analysis.
The Breker SystemVIP library has seen wide adoption in the semiconductor industry on the most complex of designs.
SystemVIP Scenario Library
Networking Gen
Automated Packet Generation
Performance Profiling
Analyze Performance Issues
Test Suite Synthesis Verification Amplification
Most commercial test suites are templated in nature: that is, a range of individual test are provided that may be configured for various design situations. Breker’s SystemVIP is based on synthesis technology that has an amplifying effect on the scenario models to significantly improve coverage and bug hunting.
Planning Algorithms, an AI technique, have been incorporated to explore the state space of the various scenarios, starting with the desired end space and working backwards to initial inputs. This technique allows for precise test execution that tracks from input to the specific states in question, which lead to more effective bug hunting with fewer tests than a more general hit-and-miss randomized approach.
Test cross combination is another synthesis technique that combines the various scenario components in a multidimensional series of tests. For example, crossing different privilege levels with branch prediction and load store scenarios, plus others, to build combined tests, increases the odds of an unusual corner case issue occurring.
Scheduling concurrent scenarios further increases the pressure on design components to reveal difficult bottlenecks in design architecture by “torturing” the device, similar to running a car engine at high revs for extended periods to reveal weaknesses.
Tests are scheduled together across threads and multicore processors that overload SoC resources, allowing the performance of the tests to be examined in a profiling window.
SystemVIP Coverage and Bugs
The SystemVIP library has been in use at various semiconductor and electronic system companies. These companies have provided coverage and uncovered bug information.
The figures below show a comparison of test density for a set of manually-derived cache coherency tests versus tests synthesized using the Breker System Coherency SystemVIP. The displayed address accesses together with read and write data demonstrate the level of coherency traffic possible with the SystemVIP.
Typical directed coherency coverage …
… vs. Breker automated coherency tests
Recent examples of bugs discovered in real designs
- RISC-V spec misunderstanding between core vendor and user
- Coherent Mesh Network (CMN) programming issues
- Misconfigured ARM CMN pin to enable coherent traffic
- DDR model unable to handle AXI “wrap” transactions
- Common cache line access reveals deadlock
- Custom instruction bugs discovered by stress tests
- Results mismatch with ultrawide address strides
- Incorrect exception for guest virtual address[63:38] = 0x1ffffff
- Bad mcause value for guest physical address[63:31] != 0x0