SystemUVM™
SystemUVM™ — Empowering UVM Engineering
SystemUVM-based Test Suite Synthesis Demo
The SystemUVM™ Concept
Functional verification engineers using UVM can enjoy a large number of benefits by synthesizing test content for their testbenches. Abstract, easily composable models, coverage-driven content, deep sequential state exploration, pre-execution randomization for test optimization and configurable reuse are just some examples of the advantages afforded by test suite synthesis.
However, a specification model is required and there are few alternatives that a UVM/SystemVerilog engineer can simply pick up and use. Enter SystemUVM™, a UVM class library built on top of Accellera’s Portable Stimulus Standard that looks and feels like SystemVerilog with UVM but enables the level of abstraction and composability required for synthesizable specification models with an almost negligible learning curve.
Introduction to SystemUVM
SystemUVM Linguistic Approach
Test Suite Synthesis is emerging as a powerful method to generate test content for UVM testbenches for large design blocks and multi-block sub-systems. However, the composition of specification models, up to now, has required engineers to learn a language such as Accellera’s Portable Stimulus Standard (PSS), an unnecessary learning curve.
This has changed with the advent of SystemUVM. SystemUVM is a class library built on top of PSS that makes it almost indistinguishable from UVM with SystemVerilog. SystemUVM provides:
- SystemVerilog consistent syntax
- UVM datatypes (e.g. uvm_transactions, uvm_reg_adapter)
- SystemVerilog procedural coding style
- The recognizable UVM RAL layer and other APIs
- An easy mechanism to layer content into UVM testbenches
- A set of verification service functions to save repeated effort
- Abstract Path Constraints, for powerful constraint management
SystemUVM-Based Test Suite Synthesis
Test Suite Synthesis opens up a number of advantages for the generation of test content for UVM testbenches, as follows:
- Easy, familiar SystemUVM™ model content generation
- Stimulus, scoreboard, coverage from one UVM-like model
- High-level constraints easier to understand and maintain
- Concurrent sequences synchronized: auto-virtual sequencer
- Predictive, up-front, high-coverage closure
- Specification coverage: pre-RTL closure, no coverage model
- End-in-mind, white-box deep sequential tests to find hard bugs
- Coverage-driven test generation pre-execution eliminates respins
- High-throughput, upfront randomization (re)use model
- Performance optimal tests easily layered into existing UVM testbench
- Easy UVM reuse across projects and verification phases
- Random emulation without simulator for accelerated test
SystemUVM-based Test Suite Synthesis empowers verification engineers to easily compose and execute tests up to 5X faster while achieving near perfect coverage to find the toughest bugs. What’s more, the tests can be reused for SoC with zero disruption to existing UVM testbenches.
SystemUVM-based Test Suite Synthesis Demo
For a full demonstration video of SystemUVM-based Test Suite Synthesis, please complete the form below.