Applying System Verification Techniques to RISC-V Subsystem Verification

This white paper details the critical transition from individual IP verification to comprehensive system-level validation in modern SoCs that use, by way of example, RISC-V cores. We examine the challenges of multi-core concurrency, memory ordering, and interrupt architectures, and we explain how Breker’s Test Suite Synthesis and SystemVIP is a robust solution for ensuring system integrity and compliance