There is no known way to guarantee that a system is secure. Vulnerabilities exist in hardware, software, and throughout the supply chain. They may exist by accident or by ignorance. They may have been inserted maliciously, or they may utilize some mechanism never before considered part of the attack plane. There is no one method […]
It has been said that there are more than 100 companies currently developing custom hardware engines that can accelerate the machine learning (ML) function. Some target the data center where huge amounts of algorithm development and training are being performed. Power consumption has become one of the largest cost components of training, often utilizing large […]
The industry is excited about RISC-V, and rightly so. It is enabling companies to take back control of their software execution environment without having to assume the huge responsibilities that come along with processor development and support of an ecosystem for it. Maybe a company wants to use a commercially developed core today, get the […]
It is unfortunate that design and verification methodologies have often been out of sync with each other, and increasingly so over the past 20 years. The design methodology change that caused one particular divergence was the introduction of design Intellectual Property (IP). IP meant that systems were no longer designed and built in a pseudo […]
It seems like ancient history now, but in the not so distant past, verification was performed by one tool – simulation; at one point in the flow – completion of RTL; using one language and methodology – SystemVerilog and UVM. That changed when designs continued to get larger and simulators stopped getting fast enough. Additional […]
New tools, languages, or methodologies can be an improvement over existing ones, or they can be enablers for something different. The recently approved Accellera Portable Stimulus Standard (PSS) can be either or both. A lot has been written recently about how PSS can be combined with constrained random verification methodologies and that demonstrates the improvement […]
The point of standards is to bring an industry together, to avoid duplication of effort, and to reduce risks associated with adoption of technology that may lock a user into a single vendor. These are some of the reasons why Breker was glad to see the creation of the Portable Stimulus working group within Accellera […]
Come one, come all to the first event of what we expect will be many –– Verification 3.0 Innovation Summit –– Tuesday, March 19, from 1 p.m. until 8 p.m. at the Levi’s Stadium Team Auditorium in Santa Clara, Calif. Meant for all of you in the chip design verification community, the event will provide […]
All of us at Breker invite https://www.dvcon.org/ attendees to step into our booth (#701) and expect to be amazed. You will see practical demonstrations of our new feature-rich Trek5 with practical examples of how the Portable Stimulus Standard can be applied to accelerate UVM coding for complex blocks and Software Driven Verification (SDV) for large […]
Let me start by laying the cards on the table – the Portable Stimulus Standard (PSS) is a language, not a methodology. Tools are not methodologies. Languages ensure a well-ordered transfer of information from which tools can be constructed. A methodology is a way of systematically breaking down and solving a problem in a manageable […]