Entries by becbrek

Breker Verification Systems’ Maheen Hamid Named to 100 Most Influential Women in Silicon Valley List by Silicon Valley Business Journal

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Honored for Her Financial Experience, Operations Management and Commitment to Entrepreneurship to Bring Change SAN JOSE, CALIF. –– May 19, 2022 –– Maheen Hamid, founder, COO and CFO of Breker Verification Systems, the leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments, was named today one of Silicon Valley’s […]

Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering

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Enhances Bug Hunting by Simplifying Specification Model Composition for Test Content Synthesis in Existing UVM Environments SAN JOSE, CALIF. –– February 28, 2022 –– Breker Verification Systems used the opening of DVCon U.S. today to unveil SystemUVM™, a framework designed to simplify specification model composition for test content synthesis with a UVM/SystemVerilog syntactic and semantic […]

NucleiSys Adopts Breker’s System Coherency TrekApp

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Advantages Include Ease of Use, Fast Setup, Considerable Verification Coverage, Flexible Scaling to Meet Future Verification Needs SAN JOSE, CALIF. –– January 25, 2022 –– Breker Verification Systems today announced Nuclei System Technology deployed its System Coherency TrekApp to ensure coherency of its configurable low-power and high-performance 32- and 64-bit RISC-V processor intellectual property (IP) […]

Breker Verification Systems Unveils System Coherency Synthesis TrekApp, Building on Its Successful Cache Coherency Test Solution

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System Coherency Synthesis TrekApp Generates High Coverage Tests to Stress Coherency, Detect Corner Cases for Range of SoC Platforms, Processors AT DESIGN AUTOMATION CONFERENCE BOOTH #2528 SAN JOSE, CALIF. –– December 6, 2021 –– Breker Verification Systems today unveiled its System Coherency Synthesis TrekApp used to generate thousands of high-coverage tests to stress cross-system coherency […]

Maheen Hamid of Breker Verification Systems Appointed to SEMI ESD Alliance Governing Council

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Breker’s COO, CFO Joins Nine Governing Council Executives MILPITAS, CALIF. –– October 19, 2021 –– The Electronic System Design Alliance, a SEMI Technology Community, today announced the appointment of Maheen Hamid, Chief Operating Officer and Chief Financial Officer of Breker Verification Systems, to its Governing Council. Hamid assumes the seat formerly held by Babak Taheri […]

Breker Launches the Synthesizable VerificationOS™ to Simplify and Streamline the Composition of High-Coverage, Portable Test Content

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Lightweight kernel provides key services and execution management of Software-Driven SoC, UVM, and Post-Silicon production verification environments SAN JOSE, CALIF. — March 1st, 2021 — Breker Verification Systems, the leading provider of advanced test content generation solutions for System-on-Chip (SoC), Universal Verification Methodology (UVM) and Post-Silicon verification environments today announced the Synthesizable VerificationOS™. The Synthesizable […]

Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis

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Developed with SiFive to Address RISC-V System Integration Validation; Generates High-Impact SoC Verification Test Suite with Minimal Manual Effort SAN JOSE, CALIF. –– December 10, 2019 –– Breker Verification Systems, the leading provider of Test Suite Synthesis tools based on the Portable Stimulus Standard (PSS), today introduced its RISC-V TrekApp, a complete, automated test content […]

Breker Verification Systems Unveils Intelligent Regression Optimization Solution to Accelerate Simulation, Emulation Execution

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New Efficiency Features Include Intelligent Coverage Targeting, Pre-Solve/Compile Test Application, RapidFire Test Scheduling SAN JOSE, CALIF. –– September 24, 2019 –– Breker Verification Systems, the leading provider of Portable Stimulus Standard (PSS)-compliant software, today announced its PSS-based Test Suite Synthesis includes a set of new efficiency features including Intelligent Coverage Targeting, Pre-Solve/Pre-Compile Test Application and […]

MEDIA ALERT: Jim Hogan Leads “Are We Experiencing a Renaissance in Chip Design and EDA?” Panel Discussion During ES Design West

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With Panelists Joe Costello, Breker, Imperas, Methodics, Metrics, OneSpin Executives SAN JOSE, CALIF. –– June 27, 2019 –– WHO: Jim Hogan, Silicon Valley venture capitalist, software and executive managing partner of Vista Ventures, LLC. WHAT: Leads a panel discussion “Are We Experiencing a Renaissance in Chip Design and EDA?” with Metrics’ Joe Costello, chairman of […]