Breker Launches the Synthesizable VerificationOS™ to Simplify and Streamline the Composition of High-Coverage, Portable Test Content
Lightweight kernel provides key services and execution management of Software-Driven SoC, UVM, and Post-Silicon production verification environments
SAN JOSE, CALIF. — March 1st, 2021 — Breker Verification Systems, the leading provider of advanced test content generation solutions for System-on-Chip (SoC), Universal Verification Methodology (UVM) and Post-Silicon verification environments today announced the Synthesizable VerificationOS™. The Synthesizable VerificationOS allows operating system-like services to be automatically embedded in test content and manages the execution of concurrent test operations, particularly critical for the verification of complex SoCs.
The Synthesizable VerificationOS will be a major part of a Breker-sponsored workshop at DVCon US on March 1st, which will also feature an interview with Mike Chin, Principal Engineer at Intel, where he discusses the need for this technology.
“Modern SoCs require functional tests that can track the highly complex corner cases created by operational concurrency in both software and hardware,” noted Adnan Hamid, Chief Executive Officer, Breker Verification Systems. “Just like software needs an OS, software-driven test content requires the Synthesizable VerificationOS to simplify composition, scale concurrent coverage and drive shift-left test content portability.”
Software engineers rely on operating systems, such as Linux®, for essential services and program execution. For software-driven SoC verification much of the same functionality is required, but in a solution that is efficient enough to be executed during the simulation or emulation of a Register Transfer Level (RTL) design. The Synthesizable VerificationOS provides this mechanism, saving hours of complicated test composition while enabling a high degree of test portability from UVM to SoC and Post-Silicon environments running on simulation, emulation and prototyping platforms.
The Synthesizable VerificationOS operates with new language features to be included in the 2.0 version of the Accellera Portable Stimulus Standard (PSS). It can also be driven from C++ and SystemVerilog UVM testbenches. It integrates essential services into test content, such as memory allocation, virtual register access, and transaction manipulation, which otherwise must be written manually as part of the test composition process. It also schedules concurrent test threads together with required resources and manages the entire verification process. This includes synchronizing software-driven tests running on multiple processors with transactions applied to the SoC ports.
The Synthesizable VerificationOS is part of a broader strategy by Breker to accelerate and increase the quality of modern SoC verification. The company has provided solutions to enable a “Single Source of Truth” which allows tests to be composed based on design intent and synthesized into reusable test content. This includes a library of configurable “TrekApps” for common scenarios. Breker’s “3D Coverage™” approach allows classic combinatorial coverage to be combined with sequential and concurrent coverage technologies that drives rigorous parallel testing to uncover complex corner case scenarios common in SoCs. The Synthesizable VerificationOS completes this strategy by enabling easily-applied, portable tests and enabling a “shift-left” verification process. Demonstrable results highlight ease-of-use and rapid adoption by engineers verifying complex chips.
Breker at DVCon US 2021
Breker will be sponsoring a workshop entitled “Functional SoC and Early Firmware Verification Using a Virtual Realization Layer” at 1:30PM PST on Monday 1st March 2021 at the DVCon US conference. Adnan Hamid will discuss the use of the Synthesizable VerificationOS for SoC Verification and the workshop will also feature Mike Chin of Intel elaborating on the verification challenges that has led to the development of this technology. More information may be found at the DVCon website.
Adnan Hamid will also be a co-presenter of the Accellera Portable Stimulus Standard (PSS) 2.0 tutorial at 9:00AM PST on the same day.
Attendees can visit the Breker virtual booth at the virtual conference, see a demonstration of the Synthesizable VerificationOS in action, and schedule further discussions with the company’s technical representatives.
About Breker Verification Systems
Breker Verification Systems is a leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms. It is the first company to introduce graph-based verification and the synthesis of powerful test sets from intent-based, abstract scenario models. Breker’s Test Suite Synthesis and TrekApp library allows the automated generation of high-coverage, powerful test cases for deployment into a variety of UVM, SoC and Post-Silicon verification environments. Case studies that feature Altera (now part of Intel), Analog Devices, Broadcom, IBM, Huawei and other companies leveraging Breker’s solutions are available on the Breker website. Breker is privately held and works with leading semiconductor companies worldwide. Visit www.brekersystems.com to learn more.
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The Synthesizable VerificationOS, TrekUVM, TrekSoC, TrekSoC-Si, TrekBox, TrekApps and SoC Scenario Modeling are registered trademarks of Breker Verification Systems. Breker Verification Systems acknowledges trademarks or registered trademarks of other organizations for their respective products.