Modern Semiconductor Verification
The last decade has seen monumental evolution in electronic device sophistication, and continued advances lie ahead. As these devices become increasingly ubiquitous to everyday life, their reliability is paramount and represents the most complex challenge faced by electronics companies. High-quality, efficient hardware verification is a critical element of modern IC design, representing, on average, approximately 75% of total Integrated Circuit (IC) development time and resources (Wilson Research 2020).
Given the continual increase in IC design size and complexity, as well as specific advances—such as Artificial Intelligence (AI), open processor instruction sets, and safety / security requirements—traditional verification methods no longer scale to modern needs. As such, the approximately $1.5B verification market (ESD Alliance 2020), is constantly evolving. Test content and testbench production has experienced the most radical evolution of all of the verification technologies over the last 20 years, and it is still this aspect of the process that causes development teams the greatest challenges. It is this area on which Breker has focused its attention, producing highly effective test suite synthesis solutions that have gained widespread adoption.
Breker Verification Systems solves challenges across the functional verification process for large, complex semiconductors. This includes streamlining UVM-based testbench composition and execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions, and providing general test content portability and reuse. Breker solutions are designed to easily layer into existing environments and operate across simulation, emulation/prototyping, and post-silicon execution platforms.
Our Trek family of products is production-proven at many leading semiconductor companies worldwide. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), Breker has earned a reputation for dramatically reducing verification schedules in advanced development environments. The company’s solutions enable design managers and verification engineers to realize measurable productivity gains, speed coverage closure, and easily reuse verification knowledge.
Breker Technology and Products
Breker’s core Test Suite Synthesis technology may be likened to design synthesis, which converts a Register Transfer Level (RTL) model of a design to a generic implementation, which is then optimized for a specific silicon platform based on characteristic constraints.
In Test Suite Synthesis, a model of a design specification, written in either the new Accellera PSS or native C++, is first exploded into a relevant state space (the potential states a design may get into). Coverage constraints are applied and Planning Algorithms—Artificial Intelligence (AI) algorithms—are used to extract generic test content. This is then applied to Breker’s Synthesizable VerificationOS™, which maps the test content to the relevant platform, schedules concurrent tests, and then executes the verification operation.
This mechanism has been proven to reduce test composition time by 5X, while increasing the effective coverage by 4X (Broadcom Case Study, Breker Website) over the equivalent manual effort at many leading semiconductor companies.
This technology may be applied directly to existing Universal Verification Methodology (UVM) block-level testbenches using TrekUVM™. The composition of sequences and higher level testbench components is greatly accelerated using the familiar abstract SystemUVM approach, coverage may be specified up-front once and then used during test generation, and many other advantages may also be applied easily in existing environments.
TrekSoC™ and TrekSoC-Si™ allow intuitive models to be developed that track deep corner-case issues at the SoC level, with or without a processor. A combination of C and transaction tests is synchronized across the SoC ports and processors, and full multi-threaded tests may be scheduled for complete system torture testing. Scenarios for SoC issues such as Cache Coherency may be leveraged from a library of apps, and even early firmware tests can be accomplished. These solutions enable test portability across simulation, emulation, prototyping, and actual silicon, eliminating redundant effort across the development flow and also across different projects with easy reconfiguration.
Both solutions come with powerful debug and design profiling mechanisms as well as coverage analysis. They are fully integrated into all leading simulators, emulators, prototyping mechanisms, virtual platforms, and final silicon testbeds.
Breker also produces a range of “apps” to provide push button solutions for common system verification problems. The System Coherency TrekApp verifies coherency across the most complex multiprocessor SoC architectures. The Power Analysis TrekApp automates the verification of power domain reset states in a multi-power domain device. The ARMv8 and RISC-V TrekApp handles comprehensive processor test issues. The Security TrekApp focuses on Hardware Root of Trust security issues in an SoC, and the Networking TrekApp produces a range of communications protocol test streams. Customers can begin testing earlier in the process, even before RTL coding is complete, and expand incrementally to realize greater coverage.
Breker has grown steadily, partnering with diverse engineering teams at leading-edge semiconductor companies. Our dynamic team shares one vision, to drive the evolution of verification technology with a single-minded focus on our customers’ success. Breker is a venture-backed company headquartered in Silicon Valley with a support network operating worldwide.
Breker is led by Adnan Hamid, named a Top Embedded Innovator by Embedded Computing Design.