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Adnan’s View
Welcome back! We all know that we’re heading into an exciting decade. Everything is going to change. The fast, easy creation of high-impact, high-coverage test content is a critical enabler, and the mechanism is here for many new complex designs.
In this newsletter, I review recent developments and look forward into 2020.
Test Suite Synthesis is as revolutionary as design synthesis and, with the help of the now standardized Portable Stimulus, provides a graph-based input scheme that allows verification intent to be easily specified without implementation detail. Now engineers can decide the coverage they need and automatically generate the tests to deliver it. Synthesis is a path for verification intent to reach existing UVM, software-driven, even post-silicon verification in a fully portable manner.
This year, PSS synthesis goes practical.
We started and will continue to demonstrate how this technology meets these future needs. We delivered the RISC-V system integration TrekApp, TrekApps for ARM integration and cache coherency, power domain testing, along with a coverage-driven, accelerated emulation use model.
See us at DVCon where we’ll talk security and safety, with more to follow through the year.
My best wishes,
Adnan Hamid
RISC-V TrekApp: Push-button RISC-V System Integration Validation
In December, we announced our RISC-V TrekApp, a complete, automated test content generator for RISC-V cache coherency and system integration testing, developed in cooperation with SiFive, the leading provider of commercial RISC-V processors.
Our RISC-V TrekApp is the first solution to address the entire RISC-V system integration problem. It targets multiple verification challenges including cache coherency and interrupt testing, and increases coverage by executing unpredictable corner case scenarios. The TrekApp works with existing UVM and software-driven verification environments and does not require the user to learn the PSS language.
SiFive’s U54-MC Platform
DVCon 2020: Practical, Effective Security Verification
This year, we will once again be visible at DVCon U.S. from March 2-4 at the DoubleTree Hotel in San Jose, Calif. We will show live demonstrations of the Breker Test Suite Synthesis technology during our “Security Verification Using Portable Stimulus Test Suite Synthesis” Short Workshop Monday, March 2, at 3:30pm. The workshop will offer a look at how to apply Test Suite Synthesis on classic security verification problems using live case studies.
Adnan will join the “New Chip Designs Create Tidal Wave of Change” panel Wednesday, March 4, at 8:30am. Moderated by Semiconductor Engineering’s Brian Bailey, this panel will discuss the future of verification, challenges we are seeing and evolving methods to deal with them.
Of course, we will demonstrate our full line of our PSS Test Suite Synthesis on real verification problems in our booth (#701).
Automated Security Verification Graph
Test Suite Synthesis, Regression Optimization and More
At the end of 2019, we delivered various papers and other detailed technical information on Test Suite Synthesis. We introduced regression optimization technology, which can be used to dramatically improve methodologies, particularly in relation to emulation performance.
Test Suite Synthesis works much like Design Synthesis. It takes an intent description and uses it to create test content without an engineer having to think about intent and implementation at the same time. This saves time normally spent crunching details and allows the tool to do what it is good at — increasing functional coverage by searching out all of the unexpected corner cases. Much like regular synthesis, constraints together with coverage goals can be set up front and used to direct test generation for specific verification platforms such as simulation and emulation and scenarios.
Comparison of Design Synthesis and Test Suite Synthesis
Regression optimization provides multiple capabilities designed to accelerate the process of regression verification for both simulation and emulation.
For emulation, this solution allows randomized test content to be solved pre-emulation. It avoids the need to recompile testbenches, accelerates the collection of coverage and debug information, and generally allows test content reactivity to not interrupt the emulation process.
The Breker Knowledge Center
Breker Verification and Portable Stimulus experts offer a range of advice and helpful hints in a series of blog posts. Here’s a sampling of the latest.
Breker Blogs
Originally from The Breker Trekker on EDACafe:
Adnan Hamid explains the Portable Stimulus Standard Landscape.
- Methodology, Language and Tools
- Interim Solutions to the Standards Gap
- Improve or Enable
- Multi-Dimensional Verification
- Methodology Convergence
- PSS and RISC-V – A Match Made In Verification
Originally from Inside Portable Stimulus on EEWeb:
Leigh Brady and Aileen Honess concentrate on explaining the fundamental concepts of the new Portable Stimulus Standard language from Accellera.
From Around the Industry
The Breker name appeared in a variety of articles this year, from the Global Semiconductor Alliance (GSA) Forum and Tech Design Forum to Semiconductor Engineering and Semiwiki.
GSA Forum:
- The Emergence of Verification 3.0 by Dave Kelf
Tech Design Forum:
- Using Portable Stimulus for Automotive Random Error Analysis by Adnan Hamid
Semiconductor Engineering:
- When Verification Leads, Experts at the Table, Part 1
- Incremental System Verification, Experts at the Table, Part 2
- Evolution Of Verification Engineers, Experts at the Table, Part 3
- Disregard Safety And Security At Your Own Peril, Experts at the Table, Part 1
- Who’s Responsible For Security Breaches? Experts at the Table, Part 2
- Tackling Safety And Security, Experts at the Table, Part 3
- The Growing Impact Of Portable Stimulus, Experts at the Table, Part 1
- Extending Portable Stimulus, Experts at the Table, Part 2
- Portable Stimulus And Digital Twins, Experts at the Table, Part 3
Semiwiki:
- CEO Interview: Adnan Hamid of Breker Systems
- Breker on PSS and UVM
- Taking the pain out of UVM
- Build More and Better Tests Faster
Technical Resources
Breker’s Website hosts downloadable whitepapers and case studies all written to help make the decision to move to PSS or ways to improve it in your chip design verification flow.
This Month’s Featured Whitepaper:
“Taking the Pain out of UVM: Leveraging Portable Stimulus to Eliminate Classic UVM Issues”
This paper demonstrates how PSS can be leveraged in UVM environments. UVM is effective for establishing common testbench coding methods, enabling reuse and improving test comprehension, though the methodology has limitations that impact complex block verification. PSS allows for many of them to be eliminated while leveraging existing testbenches. Through Breker’s tools, PSS enables a white-box approach to test authoring, allows complex multi-threaded, synchronized sequences to be generated from single scenarios, automatically provides scoreboard checks and coverage models, and improves test reuse and verification use models.
Our Featured Case Study:
Targeting Complex Power-mode Verification using Breker TrekSoC and Portable Stimulus at Broadcom, Inc.
Broadcom made use of Breker’s TrekSoC Portable Stimulus Test Synthesizer on one of its latest devices. This case study describes the verification of power domain activation mixing UVM tests and C code running on a CPU.