The Breker Buzz
The Breker Knowledge Center
Breker Verification and Portable Stimulus experts offer a range of advice and helpful hints in a series of blog posts. Here’s a sampling of the latest.
Originally from The Breker Trekker on EDACafe:
Adnan Hamid explains the Portable Stimulus Standard Landscape.
- Methodology, Language and Tools
- Interim Solutions to the Standards Gap
- Improve or Enable
- Multi-Dimensional Verification
- Methodology Convergence
- PSS and RISC-V – A Match Made In Verification
Originally from Inside Portable Stimulus on EEWeb:
Leigh Brady and Aileen Honess concentrate on explaining the fundamental concepts of the new Portable Stimulus Standard language from Accellera.
From Around the Industry
The Breker name appeared in a variety of articles this year, from the Global Semiconductor Alliance (GSA) Forum and Tech Design Forum to Semiconductor Engineering and Semiwiki.
- The Emergence of Verification 3.0 by Dave Kelf
Tech Design Forum:
- Using Portable Stimulus for Automotive Random Error Analysis by Adnan Hamid
- When Verification Leads, Experts at the Table, Part 1
- Incremental System Verification, Experts at the Table, Part 2
- Evolution Of Verification Engineers, Experts at the Table, Part 3
- Disregard Safety And Security At Your Own Peril, Experts at the Table, Part 1
- Who’s Responsible For Security Breaches? Experts at the Table, Part 2
- Tackling Safety And Security, Experts at the Table, Part 3
- The Growing Impact Of Portable Stimulus, Experts at the Table, Part 1
- Extending Portable Stimulus, Experts at the Table, Part 2
- Portable Stimulus And Digital Twins, Experts at the Table, Part 3
- CEO Interview: Adnan Hamid of Breker Systems
- Breker on PSS and UVM
- Taking the pain out of UVM
- Build More and Better Tests Faster
Breker’s Website hosts downloadable whitepapers and case studies all written to help make the decision to move to PSS or ways to improve it in your chip design verification flow.
This Month’s Featured Whitepaper:
“Taking the Pain out of UVM: Leveraging Portable Stimulus to Eliminate Classic UVM Issues”
This paper demonstrates how PSS can be leveraged in UVM environments. UVM is effective for establishing common testbench coding methods, enabling reuse and improving test comprehension, though the methodology has limitations that impact complex block verification. PSS allows for many of them to be eliminated while leveraging existing testbenches. Through Breker’s tools, PSS enables a white-box approach to test authoring, allows complex multi-threaded, synchronized sequences to be generated from single scenarios, automatically provides scoreboard checks and coverage models, and improves test reuse and verification use models.
Broadcom made use of Breker’s TrekSoC Portable Stimulus Test Synthesizer on one of its latest devices. This case study describes the verification of power domain activation mixing UVM tests and C code running on a CPU.