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Breker Verification Systems and Codasip Announce Co-operation to Drive Open, Commercial-Grade RISC-V SoC Verification Processes
Imperas Announces Partnership with Breker to Drive Rigorous Processor to System Level Verification for RISC-V
Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies
Breker Verification Systems’ Maheen Hamid Named to 100 Most Influential Women in Silicon Valley List by Silicon Valley Business Journal
Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering
Breker Verification Systems and Codasip Announce Co-operation to Drive Open, Commercial-Grade RISC-V SoC Verification Processes
/by becbrekProven Verification Leaders Collaborate on Open SoC Scenario Validation Standards, Methodologies, and Metrics
SAN FRANCISCO –– July 11, 2022 –– Breker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency, and Codasip, the leading supplier of customizable RISC-V processor IP, today announced an extensive technical collaboration to develop and improve rigorous verification processes for common RISC-V SoC scenarios.
Today’s announcement comes as Breker and Codasip demonstrate their RISC-V SoC verification and processor IP solutions at Design Automation Conference (DAC) in Booth #2528 and #1451, respectively, at Moscone West here.
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Imperas Announces Partnership with Breker to Drive Rigorous Processor to System Level Verification for RISC-V
/by becbrekWith a unified, standards-based approach to verification and Verification IP reusability, mutual customers can seamlessly transition between RISC-V processor and system level DV
Oxford, United Kingdom, July 7th, 2022 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced a partnership with Breker Verification Systems, a leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments.
With a combined approach to standards-based verification, development teams will be able to efficiently transition from RISC-V processor functional design verification (DV) right through to system level and SoC integration testing, including automated cache coherency validation.
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Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies
/by becbrekLeveraging De-Facto Standard Cache Coherency and Integration Test Solutions for Rigorous, Commercial Grade RISC-V Verification
SAN JOSE, CALIF. –– June 30, 2022 –– Breker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC integration Verification Intellectual Property (VIP) in the “TrekApps” family, today joined RISC-V International (RVI) as a strategic member.
Breker will offer its expertise in SoC verification solutions to the RVI working groups.
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Breker Verification Systems’ Maheen Hamid Named to 100 Most Influential Women in Silicon Valley List by Silicon Valley Business Journal
/by becbrekHonored for Her Financial Experience, Operations Management and Commitment to Entrepreneurship to Bring Change
SAN JOSE, CALIF. –– May 19, 2022 –– Maheen Hamid, founder, COO and CFO of Breker Verification Systems, the leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments, was named today one of Silicon Valley’s 100 most influential women by Silicon Valley Business Journal.
Hamid will be honored during the Women of Influence Award Ceremony at the San Jose Hilton Signia in San Jose, Calif., Thursday, June 16, along with other recipients selected from the private, public and nonprofit sectors. The women are business owners, executives and entrepreneurs like Hamid and community leaders, all of whom are making a mark in Silicon Valley.
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Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering
/by becbrekEnhances Bug Hunting by Simplifying Specification Model Composition for Test Content Synthesis in Existing UVM Environments
SAN JOSE, CALIF. –– February 28, 2022 –– Breker Verification Systems used the opening of DVCon U.S. today to unveil SystemUVM™, a framework designed to simplify specification model composition for test content synthesis with a UVM/SystemVerilog syntactic and semantic approach familiar to universal verification methodology (UVM) engineers.
Developed in partnership with leading semiconductor companies, Breker’s SystemUVM’s UVM-style specification model drives test content synthesis, leveraging artificial intelligence (AI) planning algorithms for deep sequential bug hunting in existing UVM environments.
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NucleiSys Adopts Breker’s System Coherency TrekApp
/by becbrekAdvantages Include Ease of Use, Fast Setup, Considerable Verification Coverage, Flexible Scaling to Meet Future Verification Needs
SAN JOSE, CALIF. –– January 25, 2022 –– Breker Verification Systems today announced Nuclei System Technology deployed its System Coherency TrekApp to ensure coherency of its configurable low-power and high-performance 32- and 64-bit RISC-V processor intellectual property (IP) designs.
“After an extensive evaluation, we choose Breker’s System Coherency TrekApp to help to ensure our design’s coherency,” remarks JianYing Peng, CEO of Nuclei System Technology. “TrekApp offers ease to use and extremely fast setup and covers broad aspect of verification from simple workload to complex scenarios that includes Dekker and Atomics tests.”
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Breker Verification Systems Unveils System Coherency Synthesis TrekApp, Building on Its Successful Cache Coherency Test Solution
/by becbrekSystem Coherency Synthesis TrekApp Generates High Coverage Tests to Stress Coherency, Detect Corner Cases for Range of SoC Platforms, Processors
AT DESIGN AUTOMATION CONFERENCE BOOTH #2528
SAN JOSE, CALIF. –– December 6, 2021 –– Breker Verification Systems today unveiled its System Coherency Synthesis TrekApp used to generate thousands of high-coverage tests to stress cross-system coherency for a broad range of SoC platforms and processors.
Based on Breker’s Cache Coherency TrekApp, the System Coherency Synthesis TrekApp uses abstract models of common and novel algorithms to automatically generate coherency test content for complex, multi-agent system platforms based on coverage directives. The TrekApp can be configured for Arm, RISC-V and other processor configurations and broad range of storage and I/O architectures.
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Breker Verification Systems Names David Kelf CEO and Adnan Hamid Executive President and CTO
/by becbrekManagement Expansion Driven by Significant Growth in Product Demand and Company Operations
SAN JOSE, CALIF. –– October 26, 2021 –– The Board of Directors of Breker Verification Systems today appointed David Kelf as CEO and Adnan Hamid as Executive President and CTO.
These changes in the management team allows Breker, the leading provider of advanced test content synthesis solutions for System-on-Chip (SoC), Universal Verification Methodology (UVM) and Post-Silicon verification environments, to meet the growing demand for its test content synthesis solutions. It also enables the team to manage rapidly expanding operations, while maintaining Breker’s technical leadership. Previously, Kelf served as Breker’s chief marketing officer (CMO) and also managed the company’s sales channel.
“As Breker’s solutions are leveraged across the semiconductor industry in many verification phases demanding technical thought leadership and pioneering solutions, our growing business activities call for a re-focused executive team,” remarks Hamid. “We are excited to have a proven industry leader and verification enthusiast such as Dave at the helm of the company as we rapidly evolve into a leading EDA player. In our years of working together, our equal commitment to customer success bodes well for our new direction.”
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Maheen Hamid of Breker Verification Systems Appointed to SEMI ESD Alliance Governing Council
/by becbrekBreker’s COO, CFO Joins Nine Governing Council Executives
MILPITAS, CALIF. –– October 19, 2021 –– The Electronic System Design Alliance, a SEMI Technology Community, today announced the appointment of Maheen Hamid, Chief Operating Officer and Chief Financial Officer of Breker Verification Systems, to its Governing Council.
Hamid assumes the seat formerly held by Babak Taheri who was CEO/CTO of Silvaco. She will serve a two-year term that runs through 2023, joining:
“The entire Governing Council welcomes Maheen,” says Smith. “She is a seasoned, accomplished executive who will offer great industry insights.”
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Breker Launches the Synthesizable VerificationOS™ to Simplify and Streamline the Composition of High-Coverage, Portable Test Content
/by becbrekLightweight kernel provides key services and execution management of Software-Driven SoC, UVM, and Post-Silicon production verification environments
SAN JOSE, CALIF. — March 1st, 2021 — Breker Verification Systems, the leading provider of advanced test content generation solutions for System-on-Chip (SoC), Universal Verification Methodology (UVM) and Post-Silicon verification environments today announced the Synthesizable VerificationOS™. The Synthesizable VerificationOS allows operating system-like services to be automatically embedded in test content and manages the execution of concurrent test operations, particularly critical for the verification of complex SoCs.
The Synthesizable VerificationOS will be a major part of a Breker-sponsored workshop at DVCon US on March 1st, which will also feature an interview with Mike Chin, Principal Engineer at Intel, where he discusses the need for this technology.
“Modern SoCs require functional tests that can track the highly complex corner cases created by operational concurrency in both software and hardware,” noted Adnan Hamid, Chief Executive Officer, Breker Verification Systems. “Just like software needs an OS, software-driven test content requires the Synthesizable VerificationOS to simplify composition, scale concurrent coverage and drive shift-left test content portability.”
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