Press Releases
Press Releases
Search the Site
Press Contact
Nanette Collins
P: +1 617.437.1822
nanette@nvc.com
Recent Posts
Breker Verification Systems’ Maheen Hamid Named to 100 Most Influential Women in Silicon Valley List by Silicon Valley Business Journal
Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering
NucleiSys Adopts Breker’s System Coherency TrekApp
Breker Verification Systems Unveils System Coherency Synthesis TrekApp, Building on Its Successful Cache Coherency Test Solution
Breker Verification Systems Names David Kelf CEO and Adnan Hamid Executive President and CTO
Breker Verification Systems Appoints Dave Kelf to Newly Created Role of Chief Marketing Officer
/by becbrekResponsibilities Range from All Aspects of Marketing to Strategic Programs, Channel Management, Portable Stimulus Standardization
SAN JOSE, Calif., Jan. 25, 2018 — Breker Verification Systems, the leading provider of Portable Stimulus, today named Dave Kelf to the newly created role of chief marketing executive.
Kelf, who most recently served as of vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions, is responsible for all aspects of Breker’s marketing activities, strategic programs and channel management. He reports to Adnan Hamid, Breker’s chief executive officer (CEO) and co-founder.
Read more
Media Alert: Breker Verification Systems to Demonstrate Portable Stimulus at DVCon India
/by becbrekTutorial Introducing Portable Stimulus Standard includes Presentation from Breker’s Adnan Hamid
SAN JOSE, CA — Aug 31, 2017 —
WHO: Breker Verification Systems, the leading provider of Portable Stimulus
WHAT: Will demonstrate practical applications of its implementation of the Early Adopter release of the Portable Stimulus Specification from Accellera at DVCon India in Booth #404, including its use in UVM-based simulation environments and embedded software testing in emulation systems.
Read more
Breker Verification Systems to Demonstrate Implementation Compliant with Accellera Portable Stimulus Draft Standard During DAC
/by becbrekWill Showcase its C++ Contribution to Standardization Effort, Displaying Practical Verification Proficiency
SAN JOSE, CA — June 15, 2017 — Breker Verification Systems, the leading provider of Portable Stimulus, will demonstrate its implementation compliant with the Early Adopter release of the Portable Stimulus Specification from Accellera at the Design Automation Conference (DAC) June 19-21 at the Austin Convention Center in Austin, Texas.
“Breker was doing Portable Stimulus before it had a name,” remarks Michael Hoyt, president of Paradigm Works and DVClub organizer. “Breker showed the semiconductor industry what could be done with a graph-based approach to chip design verification through an inspired vision and exceptional tools. The industry owes Adnan Hamid a debt of gratitude as Breker is helping simplify and streamline the verification process.”
Read more
Media Alert: Breker Verification Systems to Demonstrate Portable Stimulus Tools at DVCon
/by becbrekWill Highlight Graph-Based, Portability, Shareability: for Verification GPS
SAN JOSE, CA — February 22, 2017
WHO: Portable Stimulus Leader Breker Verification Systems
Read more
Media Alert: Breker Verification Systems to Speak on Portable Stimulus and Demonstrate Established Solution at DVCon India in Bangalore
/by becbrekSAN JOSE, CA — August 30, 2016 —
WHO: Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company
WHAT: Will exhibit in Booth 405 during the Design and Verification Conference and Exhibition (DVCon) India in Bangalore. Breker will demonstrate how its Trek family of products provides a robust, proven solution to the challenge of portable stimulus for SoC verification. Recently introduced features include a memory map viewer to aid in debug, a performance monitor to gather statistics from realistic test cases, and enhanced integration with the verification solution and flow from Synopsys, Inc. Breker’s products automatically generate multi-threaded, multiprocessor, self-verifying test cases to stress-test all features of the SoC, accelerating the chip development schedule while improving design quality. These test cases run in simulation, in-circuit emulation (ICE), FPGA prototypes, and actual silicon in the bring-up lab.
Read more
Media Alert: Breker Verification Systems to Exhibit and Demonstrate Established Portable Stimulus Solution at DAC in Austin
/by becbrekSAN JOSE, CA — June 01, 2016 —
WHO: Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company
WHAT: Will exhibit in Booth 1626 during the Design Automation Conference (DAC) in Austin. Breker will demonstrate how new features in its Trek family of products provide a robust, proven solution to the challenge of portable stimulus for SoC verification. New features include a memory map viewer to aid in debug, a performance monitor to gather statistics from realistic test cases, and enhanced integration with the verification solution and flow from Synopsys, Inc. Breker’s products automatically generate multi-threaded, multiprocessor, self-verifying test cases to verify all features of the SoC, accelerating the chip development schedule while improving design quality. These test cases run in simulation, in-circuit emulation (ICE), FPGA prototypes, and actual silicon in the bring-up lab.
Read more
Breker Verification Systems Expands Integration With Synopsys Verification Solution
/by becbrekSAN JOSE, CA — May 25, 2016 — Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company, today announced that it has enhanced the integration of its portable stimulus products with the verification solution and flow from Synopsys, Inc.
The portable, self-checking test cases generated by Breker’s Trek™ family are verified in simulation testbenches using the industry-leading Synopsys VCS® Functional Verification Solution and VC Verification IP (VIP). Any design errors uncovered by these test cases are analyzed and diagnosed using the industry-leading Synopsys Verdi® Debug Solution and Verdi HW SW Debug. The latest integration provides deeper support for Synopsys VIP, enabling the Trek-generated test cases to improve coverage in a verification environment at the SoC level, and adds integration with Verdi Coverage and Verdi Protocol Analyzer.
Read more
Agnisys and Breker Partner to Generate System-Level Portable Stimulus Sequences
/by becbrekLOWELL, MA and SAN JOSE, CA — May 24, 2016 — and Breker Verification Systems, Inc., today announced availability of an integrated solution for portable test sequences where sequences from the same description are generated for use across all verification platforms, from early-stage simulation to full-chip validation of silicon in the bring-up lab.
ISequenceSpec™ from Agnisys, provider of a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) design, verification, firmware and validation, enables users to describe programming and test sequences of a device once and generate sequences automatically. It provides a straightforward specification format to describe the sequences and generates the code that ensures synchronization between verification to validation. Users describe initialization, configuration and test sequences and ISequenceSpec automatically generates Universal Verification Methodology (UVM) models and firmware sequences usable throughout the design and verification process.
Read more
Semifore and Breker Partner to Deliver Seamless, Automated Portable Stimulus Flow
/by becbrekSAN JOSE, CA — May 23, 2016 — Semifore, Inc., the leading developer of tools for the automation of the implementation of the hardware-software interface for ASIC, SoC and FPGA-based designs, and Breker Verification Systems, Inc., the System-on-Chip (SoC) Verification Company, today announced an integration of their solutions for SoC design and verification engineers. Immediately available, the integration allows easy, flexible design and specification of SoC control registers and automatic generation of portable stimulus and tests to verify the register implementation.
Read more
Media Alert: Breker Verification Systems to Discuss Silicon Verification of 144-Processor Multi-SoC Cavium Design and Exhibit at DVCon
/by becbrekSAN JOSE, CA — February 24, 2016 —
WHO: Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company
WHAT: Will co-present a technical paper with Cavium, Inc. during the Design and Verification Conference and Exhibition (DVCon) in Silicon Valley. The presentation on “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” will discuss how the Cavium team used Breker’s Trek family of products to automatically generate interacting test cases for 144 processor cores distributed across three SoC devices in the bring-up lab. Breker’s Cache Coherency TrekApp verified full coherency across 96 of the cores while TrekSoC-Si simultaneously generated complex PCI Express (PCIe) traffic using 48 additional cores. All test cases are self-verifying and portable between simulation and hardware platforms. In addition to this talk, Breker CEO Adnan Hamid will appear on the “Redefining ESL” panel and Breker will be demonstrating its products during the DVCon exhibition.
Read more