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Recent Posts
Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios
Breker Verification Systems and Codasip Announce Co-operation to Drive Open, Commercial-Grade RISC-V SoC Verification Processes
Imperas Announces Partnership with Breker to Drive Rigorous Processor to System Level Verification for RISC-V
Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies
Breker Verification Systems’ Maheen Hamid Named to 100 Most Influential Women in Silicon Valley List by Silicon Valley Business Journal
Breker Verification Systems Expands Integration With Synopsys Verification Solution
/by becbrekSAN JOSE, CA — May 25, 2016 — Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company, today announced that it has enhanced the integration of its portable stimulus products with the verification solution and flow from Synopsys, Inc.
The portable, self-checking test cases generated by Breker’s Trek™ family are verified in simulation testbenches using the industry-leading Synopsys VCS® Functional Verification Solution and VC Verification IP (VIP). Any design errors uncovered by these test cases are analyzed and diagnosed using the industry-leading Synopsys Verdi® Debug Solution and Verdi HW SW Debug. The latest integration provides deeper support for Synopsys VIP, enabling the Trek-generated test cases to improve coverage in a verification environment at the SoC level, and adds integration with Verdi Coverage and Verdi Protocol Analyzer.
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Agnisys and Breker Partner to Generate System-Level Portable Stimulus Sequences
/by becbrekLOWELL, MA and SAN JOSE, CA — May 24, 2016 — and Breker Verification Systems, Inc., today announced availability of an integrated solution for portable test sequences where sequences from the same description are generated for use across all verification platforms, from early-stage simulation to full-chip validation of silicon in the bring-up lab.
ISequenceSpec™ from Agnisys, provider of a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) design, verification, firmware and validation, enables users to describe programming and test sequences of a device once and generate sequences automatically. It provides a straightforward specification format to describe the sequences and generates the code that ensures synchronization between verification to validation. Users describe initialization, configuration and test sequences and ISequenceSpec automatically generates Universal Verification Methodology (UVM) models and firmware sequences usable throughout the design and verification process.
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Semifore and Breker Partner to Deliver Seamless, Automated Portable Stimulus Flow
/by becbrekSAN JOSE, CA — May 23, 2016 — Semifore, Inc., the leading developer of tools for the automation of the implementation of the hardware-software interface for ASIC, SoC and FPGA-based designs, and Breker Verification Systems, Inc., the System-on-Chip (SoC) Verification Company, today announced an integration of their solutions for SoC design and verification engineers. Immediately available, the integration allows easy, flexible design and specification of SoC control registers and automatic generation of portable stimulus and tests to verify the register implementation.
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Media Alert: Breker Verification Systems to Discuss Silicon Verification of 144-Processor Multi-SoC Cavium Design and Exhibit at DVCon
/by becbrekSAN JOSE, CA — February 24, 2016 —
WHO: Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company
WHAT: Will co-present a technical paper with Cavium, Inc. during the Design and Verification Conference and Exhibition (DVCon) in Silicon Valley. The presentation on “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” will discuss how the Cavium team used Breker’s Trek family of products to automatically generate interacting test cases for 144 processor cores distributed across three SoC devices in the bring-up lab. Breker’s Cache Coherency TrekApp verified full coherency across 96 of the cores while TrekSoC-Si simultaneously generated complex PCI Express (PCIe) traffic using 48 additional cores. All test cases are self-verifying and portable between simulation and hardware platforms. In addition to this talk, Breker CEO Adnan Hamid will appear on the “Redefining ESL” panel and Breker will be demonstrating its products during the DVCon exhibition.
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Cadence, Mentor Graphics and Breker Announce Collaborative Technology Contribution to Accellera Portable Stimulus Working Group
/by becbrekSAN JOSE, Calif., Sept. 8, 2015 — Cadence Design Systems, Inc., Mentor Graphics Corporation, and Breker Verification Systems today announced that the three companies have collaborated on a technology contribution to the Accellera Portable Stimulus Working Group. The contribution leverages the combined experience of the three companies in providing portable test and stimulus solutions, and is intended to assist the Accellera Portable Stimulus Working Group in defining a system-on-chip (SoC) verification standard that offers both vertical (intellectual property to SoC) and horizontal (simulation to post-silicon) reuse of stimulus and test.
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Media Alert: Breker Verification Systems to Demonstrate Industry’s First Portable Stimulus Solution at DAC in San Francisco
/by becbrekSAN JOSE, CA — Jun 4, 2015 —
WHO: Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company
WHAT: Will exhibit in Booth 3209 during the Design Automation Conference (DAC) in San Francisco. Breker will show how its Trek family of products provides a robust, proven solution to the challenge of portable stimulus for SoC verification. Multi-threaded, multiprocessor, self-verifying test cases are generated automatically to verify all features of the SoC, accelerating the chip development schedule while improving design quality with more thorough functional verification. These test cases run in simulation, in-circuit emulation (ICE), FPGA prototypes, and actual silicon in the bring-up lab.
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Media Alert: Breker Verification Systems to Exhibit Cache Coherency TrekApp Verification Software at DVCon
/by becbrekSAN JOSE, CA — Feb 27, 2015 —
WHO: Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company
WHAT: Will exhibit in Booth 905 during the Design and Verification Conference and Exhibition (DVCon) in Silicon Valley. Breker will show how its self-contained Cache Coherency TrekApp can automatically generate portable, self-verifying, multi-threaded test cases to stress all aspects of multiple processors, caches, interconnects, and memories in an SoC design. Breker will show how these test cases can be extended to include all features of the SoC, accelerating the chip development schedule while improving design quality with more thorough functional verification.
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Media Alert: Breker Verification Systems to Exhibit TrekUVM and TrekSoC Verification Software at ARM TechCon
/by becbrekSAN JOSE, CA — Sep 30, 2014 —
WHO: Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company
WHAT: Will exhibit in Booth 170 during ARM TechCon in Silicon Valley. Breker will show how automatic generation of portable, self-verifying, multi-threaded test cases accelerate chip development schedules while improving design quality through more thorough functional verification.
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Media Alert: Breker Verification Systems to Present in Two Tutorials, Exhibit TrekUVM and TrekSoC Verification Software at DVCon India
/by becbrekSAN JOSE, CA — Sep 23, 2014 —
WHO: Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company
WHAT: Will exhibit in Booth 12 during the first Design and Verification Conference and Exhibition (DVCon) in India. Breker will show how chip development schedules can be accelerated while improving design quality through more effective functional verification.
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Media Alert: Breker Verification Systems to Demonstrate TrekSoC SoC Verification Software, Synopsys’ Verdi Advanced Debug Solution Link at Design Automation Conference
/by becbrekSAN JOSE, CA — May 28, 2014 —
WHO: Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company
WHAT: Will exhibit in Booth #2602 during the 51st Design Automation Conference (DAC). It will demonstrate a link between TrekSoC™, SoC verification software that automatically generates multi-threaded, self-verifying C test cases to run on an SoC’s multiple heterogeneous embedded processors, and Synopsys’ Verdi® solution, the industry leading, open debug platform.
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