Overview
Breker Products and IP
The Breker tool suite and SystemVIP have been proven in production at many leading semiconductor companies worldwide, earning a reputation for dramatic verification schedule reduction in advanced development environments. Breker’s solutions enable design managers and verification engineers to realize measurable productivity gains through GRAPH-based scenario description, speed coverage closure by PORTING the same tests across verification platforms, and easily SHARE verification knowledge.
TrekUVM
TrekUVM uses the same scenario model format to generate Universal Verification Methodology (UVM) test cases for transactional testbenches, all but eliminating the notorious complexity of UVM sequence authoring.
TrekSoc
TrekSoC helps customers develop intuitive models based on the PSS to describe the verification space, and then use these models to automatically generate SoC test cases including stimulus, expected results and coverage detail.
TrekSoc-Si
TrekSoC-Si enables all of the testbench capability contained in TrekUVM and TrekSoC to be applied to hardware verification solutions including Emulation, Prototyping Systems and to the final device, post-fabrication.
SystemVIP
- The System Coherency SystemVIP verifies system-level coherency in a multicore SoC.
- The RISC-V CoreAssurance SystemVIP provides the complete range of tests for the entire RISC-V core verification stack.
- The RISC-V SoCReady SystemVIP provides a comprehensive range of unique SoC tests specifically designed to thoroughly evaluate a RISC-V SoC for correct operation.
- The Arm SoCReady SystemVIP provides a comprehensive range of unique SoC tests specifically designed to thoroughly evaluate an Arm-based SoC for correct operation.
- The Security HRoT SystemVIP synthesizes test content to verify IC protected regions.
- The Power Management SystemVIP automates the verification of power domain shutdown and bringup.
TrekDAE
The Design Analysis Environment user interface provides unique visual graph construction, graph visualization, and multi-threaded runtime test inspection capabilities. It operates across all of the Breker tool suite and TrekApps, enabling a consistent use and feel for the tools. The new visual graph editor allows for fast scenario construction and comprehension.
Scenario Modeling
The entire tool suite makes use of graph-based scenario models created using either the new Accellera Portable Stimulus Standard DSL or C++ formats, or coded in native C++. The models may also be entered using the Breker visual editor, or generated from one of the TrekApps. These modeling options provide easy methods to build powerful and complete models of verification intent.