Core & SoC Integrity FASTApps
Automated Test Generation for RISC-V and other Processors
Integrity FASTApps™ Key Benefits
Series of quick, easy to use, high coverage, push button test generators for complex scenarios for use by processor developers and SoC integrators alike
Particularly applicable to RISC-V projects where they can save a lot of time in difficult areas such as interrupt/exception testing, load store integrity, memory protection, etc.
Test synthesis benefits: works on all verification platforms and final silicon, finds functional bugs and performance bottlenecks, easy to add custom instructions, etc.
Integrity FASTApps Overview
Breker is well known for its series of TrekApps that provide pre-defined tests, or SystemVIP, for common, hard-to-verify scenarios primarily targeting complex blocks, sub-systems, and full System-on-Chips (SoCs). For example, the company’s cache coherency TrekApp has become a standardized test in many semiconductor development flows.
There exists a need for test sets that target more specific issues across processor cores and both simple and complex SoCs. This is particularly pertinent for RISC-V processor cores as they cover scenarios that go beyond basic compliance and micro-architectural verification, not provided through any other sources. Breker has broken out a series of focused tests from its larger TrekApps, and is now providing these as a portfolio of processor core and SoC integrity tests.
These FASTApps may be configured for a wide variety of design and platform architectures and enable automated, push button testing that replaces many engineering months of manual composition. They provide in-depth, commercial-grade, high-coverage for scenarios that represent major verification challenges.
The RISC-V Open Instruction Architecture (ISA) presents new verification challenges. Processor core verification is notoriously complex, as demonstrated by the level of investment from tradition processor providers such as Arm, Intel and others. In addition, new capabilities such as the provision of custom instructions increase these verification challenges exponentially. The many organizations creating RISC-V processors cannot hope to perform the same level of verification as the major providers, suggesting the need for automated test generation.
RISC-V verification can be broadly broken up into ISA compliance testing at the base level, full micro-architecture testing, and integration / performance validation. The Breker Integrity FASTApps target hard to test issues in the second and third categories that are not well covered by other test providers. They have the same degree of automation and high coverage as Breker’s larger TrekApps and are applicable to both core developers wishing to ensure high-quality processors, and core integrators who want to validate processor integrity and performance in situ on their SoCs.
Included in the Breker FASTApps Portfolio
|Random Instructions||Do instructions yield correct results|
|Register/Register Hazards||Pipeline perturbations dues to register conflicts|
|Load/Store Integrity||Memory conflict patterns|
|Conditionals and Branches||Pipeline perturbations from synchronous PC change|
|Exceptions||Jumping to and returning from ISR|
|Asynchronous Interrupts||Pipeline perturbations from asynchronous PC change|
|Privilege Level Switching||Context switching|
|Core Security||Register and Memory protection by privilege level|
|Core Paging/MMU||Memory virtualization and TLB operation|
|Sleep/Wakeup||State retention across WFI|
|Voltage/Freq Scaling||Operation at different clock ratios|
|Core Coherency||Caches, evictions and snoops|
|Random Memory Tests||Test Cores/Fabrics/Memory controllers across DDR, OCRAM, FLASH etc|
|Random Register Tests||Read/write test to all uncore registers|
|System Interrupts||Randomized interrupts through GIC/CLINT interrupt controller|
|Multi-core execution||Concurrent operations on fabric and memory|
|Memory ordering||For weakly order memory protocols|
|Atomic operation||Across all memory types|
|System Coherency||Cover all cache transitions, evictions, snoops|
|System Paging/MMU||System memory virtualization|
|System Security||Register and Memory protection across system|
|Power Management||System wide sleep/wakeup and voltage/freq scaling|
Also included are end-to-end test capability for subsystems moving to full SoCs. Early Firmware test is also possible using the included Breker VerificationOS. All of these tests may be scheduled together to fully stress test both the processor core and the SoC.
Leverage the Power of Test Suite Synthesis
The Breker FASTApps have all the benefits of the full system-integrity apps leveraging the power of Test Suite Synthesis, including:
- Complete and easy configurability to fit with a broad range of design architectures
- Operation on all execution platforms including virtual platforms, UVM block/sub-system simulation, SoC software-driven simulation, emulation and prototyping, and final silicon
- Easy to incorporate custom instruction verification with the rest of the tests
- High coverage, torture testing through the use of AI planning Algorithm generation
- 3-D coverage through concurrent, multi-test scheduling to uncover corner case issues
- Execution profiling to identify bottlenecks and performance/power issues
- Advanced debug to pin-point test failures quickly in the context of the platform
- Coverage-driven, pre-execution randomization for seamless emulation and prototyping
- Rapid, quality verification leveraging test experience from hundreds of projects.
The Breker FASTApps can be easily adopted, installed, and applied regardless of verification environment, with minimal set up and integration time.