Power Management TrekApp
Power Management Verification
Automatic generation of a large number of tests that fully exercise the power state protocols across an SoC
Visual test inspection tools that highlight the cause of any bugs for further analysis using an integrated debug environment
Visual coverage analysis that highlights areas tested as well as parts of the device that may be unreachable or hard to analyze
Power Domain Verification Issues
Modern Systems on Chips (SoCs) make use of multiple power domains that may be shut down to conserve power when not in use. Processors are designed to save power while in an idle state and then rapidly start up power intense sections as needed. Starting up these domains often requires a complex reset sequence that must be initiated without disrupting other components. Often several domains can be starting up or powering down coincidentally, and this activity must be handled while the rest of the device operates smoothly.
Possibly the most dramatic example of these SoCs are those used in mobile cellphones. These battery-powered, power-sensitive devices rely on successful power management to shut off a number of components that are not in use for the majority of their operational period and then rapidly start them up when they are called upon.
When verifying these SoCs, the power switching protocol must be fully exercised across all of the power domains switching randomly while the rest of the device is still running. The chance of a corner case bug is high in this case, and many thousands of tests are required to uncover these.
Creating these tests is a time consuming and error prone task, and it is therefore an ideal application for a Breker TrekApp designed to exercise the power state protocol together with the rest of the device in a random nature to catch these complex bug conditions.
The Breker Power Management TrekApp
The Breker Power Management TrekApp uses standard power cycle state machines, which may be coded in a variety of different ways, to derive a test scenario model. It then synthesizes C tests for processors and transaction tests for I/O ports, interrupts and other access points to exercise the power state protocols of all the power states, while also running other functional tests. It is designed to cover complex, corner case scenarios, which would be hard to produce by hand, thereby uncovering difficult to detect issues.
The essence of the TrekApp is the ability to input power cycle state machines in standard forms. This may be accomplished by creating a graph of the state machine either using a visual editor or texturally in the PSS language. It may also be accomplished by coding up the state machine in a state table, a common method employed by engineering teams. The Power Management TrekApp will take as input a state table and generate a graph from this automatically.
From this graph-based model of the power transition modes, a broad range of tests are synthesized that exercise the graph in a large variety of ways. The single graph may generate C-based tests to drive the processor instigating the power cycle mode, along with synchronized tests on the I/O ports of the device. These tests by be layered into the functional verification scenarios of the test plan, such that the entire system may be exercised fully, with a broad range of difficult timing and operational scenarios covered.
The synthesized tests may be viewed as they execute on the test map viewer. This allows test execution to be monitored and for the root cause of any failure points to be determined quickly. From this point a standard debugger may be employed to track hardware failures and resolve the issue quickly.
The Power Management TrekApp provides 1000s of tests that would be resource intensive and error prone to create by hand. It allows for single scenario models to synthesize synchronized tests across the entire block. These powerful test sets can detect corner case issues that are very difficult to predict in advance, and has been proven on multiple designs to find complex big conditions.