Breker RISC-V TrekApp
Automates complex system integration verification, including system cache coherency, enabling configurable push button test generation
Accelerates system-level RISC-V processor validation, including instruction extension verification
Drives high-coverage closure by examining complex corner-case scenarios for RISC-V SoCs on simulation, emulation, post silicon, and virtual platforms
RISC-V Verification Challenges
The RISC-V Open Instruction Set Architecture (ISA) represents a major discontinuity in the semiconductor industry. While it provides significant benefits to processor users and providers alike, it also creates some new challenges, most related to verification.
The RISC-V open instruction set enables several advantages over proprietary ISAs, for example:
- Any company can develop its own processor hardware that can work with a range of software packages and tools delivered by other parties.
- Any company can develop and deliver specialized processor IP for sale that can operate with third-party software.
- It is possible to extend the standard ISA with specialized instructions or operations, or even use the ISA for specialized processing.
SiFive U54-MC RISC-V Multicore Processor. Courtesy SiFive
These advantages come with unique verification requirements. Instruction set compliance to the standard is critical and has been a focus of the RISC-V Foundation and multiple verification companies. However, the verification of inherent issues with standard RISC-V processor subsystem integrations, such as general connectivity, cache coherency, interrupt management, etc., have been left as an exercise for the end user.
Furthermore, as was discovered with other configurable processors, adding custom instructions to the standard ISA has its own verification issues. An additional instruction has the potential to disrupt the operation of the standard ISA and this must be checked carefully. As such, the verification of the new instructions cannot be performed in isolation; it must be checked in a modular fashion together with the rest of the subsystem and compliance tests.
The Breker RISC-V TrekApp
The Breker RISC-V TrekApp provides a complete, automated platform for RISC-V SoC testing, eliminating the need to develop a large amount of verification test content for UVM and Software-Driven flows when integrating RISC-V processors onto SoCs. The TrekApp provides rigorous, high-coverage test content for simulation, emulation, and other platforms, and provides full SoC debug and profiling.
The RISC-V TrekApp provides:
- Configurability for a broad range of SoC variants
- Complete integration and connectivity testing for RISC-V processors
- Complete Cache Coherency testing for a variety of configurations
- Interrupt mechanism testing
- Modular instruction extension verification
- Connection to multiple instruction compliance suite test suites
- System performance and power profiling
- Complete coverage information and coverage-directed testing
- Functional test inclusion (PSS, SystemVerilog/UVM, SystemC, and C/C++)
- Cooperation with other TrekApps, such as Power Domain and Security
- Operates on standard simulators, emulators, prototyping/virtual platforms, plus final silicon
- Full SoC debug environment, integrated with leading environments including Verdi
- Fully automated, does not require PSS or SystemVerilog/UVM knowledge
SiFive Cooperation on the RISC-V TrekApp
The RISC-V TrekApp was developed in cooperation with SiFive, the leading provider of commercial RISC-V processor IP and silicon solutions and a Breker test synthesis user. The RISC-V TrekApp was validated first on SiFive processors and is in use by multiple processor developers to test the integration of their custom devices.
“Working with Breker to develop the RISC-V TrekApp over the past year has been very rewarding. As RISC-V adoption continues to grow, support from design tool providers like Breker is key to accelerating time to market and assuring SoC quality.”
— Mohit Gupta, Vice President and General Manager of the SiFive IP Business Unit
RISC-V TrekApp Test Content
Using the RISC-V TrekApp, it is possible to integrate a compliant RISC-V processor onto a range of SoC platform architectures, and within a short time perform all of the necessary tests to ensure the processor is ready to run.
RISC-V TrekApp Root Graph
The TrekApp provides a complete system integration test for RISC-V processors using Test Suite Synthesis. A configurable test content generator for UVM and Software Driven Verification (SDV) environments, it targets a range of system verification challenges that otherwise require months of manual test authoring. It enables users to integrate a compliant RISC-V processor onto an SoC platform and perform all necessary tests to ensure the platform is ready to run without the need to learn the PSS language.
Features include interrupt mechanism testing, modular instruction extension verification, and links to multiple compliance test suites. A comprehensive full debug environment highlights tests that fail—including memory map and key register detail—and interfaces with common debuggers such as Synopsys’ Verdi® SoC Debug Platform for extended analysis.
SoC operational profiling is accomplished using the TrekApp by scheduling many multi-threaded tests together. This allows design performance and power analysis for an early indication of general design operation. Extensive coverage information reveals how much of the subsystem functionality was tested and permits coverage-directed test generation for high-impact verification.
The RISC-V TrekApp results can be combined with general functional verification tests written in PSS, SystemVerilog, UVM, SystemC, and C/C++ for a complete, cross-coverage test environment. It does not require knowledge of PSS, SystemVerilog, or UVM languages and may be used in a fully automated fashion.
The RISC-V TrekApp can be used with other TrekApps such as Power Domain, Security, and additional common SoC verification functions. It operates on all standard simulators, emulators, rapid prototyping systems, and virtual platforms, as well as post-silicon validation environments.
A cache coherency test suite enables automated systematic testing of data consistency and cache state transitions across all caches (L1/L2/L3 snoop filters) for multi-core/multi-cluster designs with I/O coherent interfaces such as PCI Express. Integration with fabrics, memory controllers (DDR and HBM) are stress tested, as are atomic and other special memory accesses. For instruction extension verification, verification tests can be written in PSS, SystemVerilog, UVM, and/or C/C++. These tests can be easily amalgamated with the system integration test suite for complete, diverse scenario examination to confirm that no additional instructions will impair smooth operation of the SoC.
The RISC-V TrekApp cooperates with Breker’s leading test suite synthesis solutions.