RISC-V CoreAssurance
RISC-V CoreAssurance SystemVIP
RISC-V Automated Core Verification with Synthesis Amplification
Broad stack
Broad stack of core tests from randomized microarchitectural to system integration integrity
Synthesis backbone
Synthesis backbone drives high coverage, corner case bug hunting, performance profiling, extensibility
Portable
Self-checking content portable across simulation, emulation, and post-silicon, with debug & coverage analysis
RISC-V Core Verification Challenges
The RISC-V open Instruction Set Architecture (ISA) offers huge opportunities for processor developers. However, to achieve the quality expectations set by Arm and X86, RISC-V cores require an inordinate amount of verification, including capabilities uncommon on other blocks. ISA customization further compounds this verification requirement.
RISC-V CoreAssurance SystemVIP Layered Testing
The verification of a RISC-V processor core should include a “stack” of scenarios. Breker’s RISC-V CoreAssurance SystemVIP uniquely provides this complete scenario range.
In general, a processor core needs to be evaluated for basic operation, followed by compatibility with the RISC-V ISA instructions, and an extensive micro-architectural test. Often this level of testing may be partially fulfilled using intelligent random instruction generation.
Once these basic functions have been verified, a range of tests that check the integrity of the core should also be applied. Eighty percent of processor operations consist of load-store activity, and this must be thoroughly evaluated, including efficient register and memory access at performance without hazards. Exception handling and complex interrupt patterns, varying privilege levels, pipeline perturbations, and more. Core level coherency testing, paging and security (PMP) can also be included, if appropriate. Finally, the internal performance of the core should be checked for issues.
RISC-V CoreAssurance Functionality*
| Random Instructions | Do instructions yield correct results? |
| Register/Register Hazards | Pipeline perturbations due to register conflicts |
| Load/Store Integrity | Memory conflict patterns from PC change |
| Conditionals and Branches | Pipeline perturbations from synchronous PC change |
| Exceptions | Jumping to and returning from ISR (Interrupt Service Routine) |
| Asynchronous Interrupts | Pipeline perturbations from asynchronous PC change |
| Privilege Level Switching | Context switching |
| Core Security | Register and memory protection by privilege level |
| Core Paging/MMU | Memory virtualization and TLB (Translation Lookaside Buffer) operation |
| Sleep/Wakeup | State retention across WFI (Wait For Interrupt) instructions |
| Voltage/Freq Scaling | Operation at different clock ratios |
| Core Coherency | Caches, evictions, and snoops |
*Functionality included in RISC-V CoreAssurance and System Coherency SystemVIPs
SystemVIP Test Suite Synthesis Amplification
The RISC-V CoreAssurance SystemVIP provides the complete range of tests for the entire RISC-V core verification stack. Starting with randomized instruction generation and microarchitectural scenarios, RISC-V CoreAssurance includes unique tests that check all integrity levels, ensuring the smooth application of the core into an SoC, regardless of architecture, and the evaluation of possible performance and power bottlenecks, as well as functional issues.
The SystemVIP can be easily extended to allow custom RISC-V instructions to be fully incorporated into the complete test suite, crossed with other tests. The SystemVIP is fully self-checking and incorporates debug and coverage analysis solutions. It may be ported across simulation, emulation, prototyping, post-silicon, and virtual platform environments.
The SystemVIP is built upon Breker’s Test Suite Synthesis platform. The platform allows for a high degree of scenario and functional coverage, together with corner-case bug-hunting far more effective than what is possible with traditional, template driven test generators. Find out more about test suite synthesis amplification.