RISC-V SoCReady
RISC-V SoCReady SystemVIP
Off-the-Shelf RISC-V SoC Verification with Synthesis Amplification
Comprehensive
Comprehensive test suite to test common, complex functional SoC operations and performance profiling
Synthesis backbone
Synthesis backbone drives high coverage, corner case bug hunting, performance profiling, extensibility
Portable
Self-checking content portable across simulation, emulation, and post silicon, with debug & coverage analysis
RISC-V Verification Challenges
The RISC-V Open Instruction Set Architecture (ISA) allows for the development of standardized processor cores by any team for a broad variety of applications. While this represents a major opportunity for many organizations, the verification of these devices and the System-on-Chips (SoCs) in which they operate, remains a significant challenge.
RISC-V SoCReady SystemVIP Description
Breker’s RISC-V SoCReady SystemVIP provides a comprehensive range of unique SoC tests specifically designed to thoroughly evaluate a RISC-V SoC for correct functional and performance operation. The SystemVIP exercises the core or cores within the context of the SoC, manipulating SoC components to ensure correct functionality. Built on top of Breker’s Test Suite Synthesis, the SystemVIP includes synthesis technologies that amplifies test coverage and corner case detection to find the most obscure of functional and performance bugs.
The SystemVIP is fully portable across a range of execution platforms (simulation, emulation, prototyping, post-silicon and virtual platforms) and can be configured and extended for many architectures. All tests are self-checking, include debug and coverage information, and are coverage-driven to allow upfront selection of required coverage. The SystemVIP comes with an integrated debugger-profiler for system-level analysis and scenario coverage views.
RISC-V SoC Verification Functionality*
| Random Memory Tests | Test Cores/Fabrics/Memory controllers across memory types |
| Random Register Tests | Read/write test to all uncore registers |
| System Interrupts | Randomized interrupts through CLINT |
| Multicore Execution | For weakly-ordered memory protocols |
| Atomic Operation | Across all memory types |
| System Coherency | Cover all cache transitions, evictions, snoops |
| System Paging/IOMMU | System memory virtualization |
| System Security | Register and memory protection across system |
| Power Management | System-wide sleep/wakeup and voltage/frequency scaling |
| Packet Generation | Generating networking packets for I/O testing |
| Interface Testing | Analyzing coherent interfaces including CXL & UCle |
| SoC Profiling | Layering concurrent tests to check operation under stress |
| Firmware-First | Executing SW on block or subsystem without processor |
*Functionality included in RISC-V SoCReady, System Coherency, and other SystemVIPs
The comprehensive test suite includes a range of load store functional, performance and hazard evaluation, interrupt and exception testing, various memory verification processes, such as memory ordering, atomic instructions, and others. Multicore operation is also evaluated along with coherency and paging testing, as required. Functional bugs are evaluated, as well as issues related to performance bottlenecks and other system integrity problems.
The RISC-V SoCReady SystemVIP works in conjunction with other Breker SystemVIP components to build complete verification environments that fully evaluate RISC-V SoCs. The SystemVIP is commonly used by RISC-V core end users to ensure that the core itself adheres to the RISC-V ISA, and to core producers to verify that the core will operate in the context of a full SoC with all subsystem support components.
SystemVIP Test Suite Synthesis Amplification
The SystemVIP is built upon Breker’s Test Suite Synthesis platform. The platform allows for a high degree of scenario and functional coverage, together with corner case bug hunting far more effective than what is possible with traditional, template-driven test generators. Find out more about test suite synthesis amplification.