Trek Suite Overview
Breker Trek Suite
Streamlining UVM-based testbenches for IP verification
Synchronizing software and hardware tests for large system-on-chips (SoCs)
Simplifying test sets for hardware emulation and post-fabricated silicon
Breker’s solutions enable test reuse across simulation, emulation, prototyping and actual silicon, eliminating redundant effort across the development flow. The Breker “Trek” suite solves challenges across the functional verification process for large, complex semiconductors.
Based on Accellera’s Portable Stimulus Standard (PSS), Breker’s TrekSoC and TrekSoC-Si help customers develop intuitive models to describe the verification space, then use these models to automatically generate SoC test cases including stimulus, expected results and coverage detail.
TrekUVM uses the same scenario model format to generate Universal Verification Methodology (UVM) test cases for transactional testbenches, all but eliminating the notorious complexity of UVM sequence authoring.
These products also work with the Breker TrekApps for specific automated verification solutions.
The Breker family of products and apps is proven in production at many leading semiconductor companies worldwide. As a leader in the development of the PSS, Breker has earned a reputation for dramatically reducing verification schedules in advanced development environments. The company’s solutions enable design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easily reuse verification knowledge.