Seamless SoC test portability across simulation, emulation, prototyping and fabricated silicon
Visibility into the hardware testing process to analyze coverage, debug and scenario execution
Rerun UVM Portable Stimulus tests without simulation-time test generation, significantly accelerating process
Testbench Issues for Hardware Verification Platforms
Modern verification is no longer restricted to simulation. As a device progresses through SoC testing, it is common to leverage emulation systems, rapid prototyping solutions, and ultimately, after device fabrication, the chip itself running on a test board.
These differing engines have created problems for testbenches due to the complexity of porting tests from simulation to these other solutions. Running UVM tests on an emulator, for example, is difficult as they must be executed on a simulator running in lockstep to the emulator, with a resulting loss in performance. Reusing emulation SoC tests on the actual silicon post-fabrication also presents issues given the lack of visibility into the chip itself. Analyzing coverage and performing debug on any of these systems is cumbersome.
TrekSoC-Si solves these problems by using the portable nature of Portable Stimulus, operating on the powerful TrekSoC environment, interfaced directly to the hardware solutions.
Hardware Verification with TrekSoC-Si
TrekSoC includes the necessary elements to connect Portable Stimulus tests to hardware verification solutions such as emulators, rapid prototyping solutions and fabricated silicon. This is accomplished with no change whatsoever to the tests used during simulation, providing portability to the hardware solutions with minimal effort.
Efficient Emulation Test Process
Creating tests for emulation has always been difficult. There is a desire to reuse tests from either the SoC or IP block-level simulation environments, but the lack of portability of these tests makes this difficult. In addition, using constrained random tests on an emulator is troublesome as the SystemVerilog advanced language constructs often cannot be executed directly on an emulation box.
TrekSoC-Si gets around this by allowing the more abstract random tests to be synthesized in advance of emulation execution. Ten synthesizer licenses are included with every runtime emulation interface to allow for the large number of emulation tests to be generated up front in proportion to the accelerated nature of emulation execution. Co-simulation with the emulator is no longer necessary.
The Portable Stimulus methodology enables a large number of tests to be generated that can exercise a very large number of possible corner case scenarios. TrekSoC is an ideal tool to create large-scale complex test sets that drive the SoC Under Test in all kinds of stressful and complex ways, hard for a test designer to invent. This is a perfect marriage with emulation, which when unimpeded by the testbench generation process, has the horsepower to run many millions of these tests.
TrekSoC-Si has been interfaced and used successfully in very complex production environments with the three market leading emulators, Synopsys ZeBu, Cadence Palladium, and Mentor Veloce. Its agnostic approach to the different emulators allows for easy switching between design flows without testbench update.
Post-Fabrication Device Bring-Up and Rapid Prototyping
The other major use of TrekSoC-Si is for testing the final device after fabrication, or on a rapid prototyping solution. In these situations, easy visibility into the device becomes an issue. TrekSoC-Si has been set up to automatically make full use of the device JTAG interface, as well as the hardware ports, to provide the same level of visibility into the device as can be achieved using simulation. All of the respective tools available for up stream verification may also be used at the end of the process, making bug detection and coverage analysis easy. The TrekSoC-Si solution may be used alongside the native software development environment and other test boards.
The portable nature of the PSS tests also allows for the successful sharing and reuse of tests from earlier in the verification process, including UVM sequences synthesized for block level testing. Any SoC tests that were run during simulation or emulation may be rerun with no additional porting effort, to provide a full and complete silicon validation.
TrekSoC-Si is a perfect companion to hardware verification systems and is critical when validating silicon post-fabrication. Leveraging the powerful TrekSoC test synthesis environment across these devices allows for vastly complex test scenarios to be evaluated quickly and easily. This has been production proven on multi-media, communications and processor tests by numerous leading electronics companies.