TrekSoC
TrekSoC™: Simplifying System-on-Chip (SoC) Verification Complexity
Benefits
Synchronized, multi-threaded tests synthesized from operational scenarios, for simulation or emulation
Manipulation of system-level resources to fully stress the design and maximize coverage
Easy visualization of system-level coverage and tests; integration with standard debug environments
Unwieldy SoC Verification
Thorough SoC verification is notoriously hard to achieve. Synchronizing multi-threaded software and hardware workflows, effectively exercising system resources, and rapidly deriving comprehensive test sets for meaningful coverage are all challenging tasks. This is further compounded by the lack of test portability between simulation, emulation and actual silicon, as well as an inability to reuse tests from other verification projects.
As SoC devices get larger and more complex, verification is becoming an all-consuming part of the development process. Breker’s TrekSoC addresses the needs of the SoC verification team by dramatically reducing the complexity associated with this process. Already in use today at a many leading semiconductor and electronic system producers, TrekSoC has been proven on some of the most complex devices in production.
TrekSoC: A Proven Approach to SoC Verification
TrekSoC leverages an abstract representation of test scenarios, described using comprehensible, graph-based models based on the Accellera Portable Stimulus Standard (PSS) DSL and/or C++ formats, or models coded in native C++. These test scenarios are then used to generate C/SystemVerilog/UVM test sets that may be applied as multi-threaded software tests across the processor(s) synchronized with hardware transactions to the various I/O ports of the device.
TrekSoC’s Efficient, Powerful Verification Capabilities
TrekSoC automatically synthesizes test cases that target system-level interactions synchronized with hardware transactions, based on an easy to understand scenario model. These aggressive and complex test cases focus on the verification of concurrent, coherent, and multi-threaded capabilities in the SoC. They are self-verifying and designed to run efficiently in simulation or on hardware verification platforms.
The scenario model is synthesized into both software C tests to be run on the embedded processor(s) and hardware transactions that drive the I/O ports of the SoC. Synchronization between processor execution and testbench transactions is automatic.
Decisions on the randomization of operations are made at compile time rather than execution time. This maximizes speed and minimizes embedded memory usage for the test cases.
In simulation, the embedded processors can communicate with TrekSoC through a memory-mapped mailbox. When a test case is generated, corresponding testbench transactions are also issued based on predetermined execution points. This mailbox mechanism is useful for other tasks as well such as managing debug tracing and “Trickboxing,” back-door memory accesses to offload data checking. The system includes an out-of-the-box memory allocation test, which is designed to stress test the system by providing weak allocation scenarios.
TrekSoC provides a novel runtime display showing how the C test cases execute on multiple threads across multiple processors. Progress through each driver scenario and each application scenario is shown visually. This helps the user to understand and document the test case, and to debug when the test case uncovers an SoC design bug.
TrekSoC: Clear, Familiar Scenario Modeling
TrekSoC makes use of scenario models written using the Accellera PSS C++ or DSL standard, or coded in native C++. These models are graph-based in nature, designed to be extremely easy to learn, understand and use.
The scenarios are described in layers, with randomized services being passed up through the layers, and constraints being driven down. The tool provides a series of generic system services in a Hardware Software Interface (HSI), extensible to provide SoC specific information, such as memory maps, bus functional models (BFMs) and system management operations.
The TrekSoC hierarchy of HSI features has been designed to mimic the hierarchy of services provided by a Linux kernel. This allows for a simple software metaphor that unifies all scenario models.
This hierarchy of scenarios is used to generate SoC tests. Each test, written out as C code for each of the processors within the SoC, takes the form of a constrained-random micro-kernel running constrained-randomized applications. TrekSoC makes random decisions about services in order to stress system interactions. This strategy yields individual test cases that are efficient, repeatable and simple to debug while allowing sophisticated decisions to be made for each of the services.
TrekSoC Scenario Layers
The generic system services available to the scenario models include:
| TrekSoC Services | Features |
|---|---|
| Memory Management | Allocates/frees memory buffers on demand
|
| Register Access | Allows scenario models to request randomization, writing and checking of register value
|
| Scheduler | Enables tasks to be flexibly scheduled sequentially
|
| Interrupts and Polls | Automatically generates interrupt handlers and non-blocking poll loops |
| System Management | Randomly switches clocking and power modes (scenario models may ask for a specific device to be powered up for the duration of an operation, possibly allowing for intermittent power downs during the operation to test state retention) |
| Testbench Actions | Allows scenario models to request arbitrary testbench activity to drive and check I/O interfaces or other testbench events |
| GPIO | Allows scenario models to request specific system GPIO routings |
| Debug Facilities | Allows scenario models to log various levels of diagnostic messages through automatic generation of diagnostics on thread progress and memory state |
| Data Checking | Allows scenario models to request checking of memory data buffers against an array of expected data |
| Timing Checks | Allows scenario models to request checking that the elapsed time between two events falls within a specified range; timing checks may be implemented using either elapsed simulation time or, if available, an onboard timer |
The flexible architecture of TrekSoC enables it to be integrated into multiple types of verification environments. It may be used on devices with full processor modeling or sub-system models where each processor is replaced by a bus functional model (BFM) directly driven by transactions. This may be done to improve simulation speed or to provide additional test control or observability. Either way the same scenario models are used. This dynamic flow can also be used to reproduce failing test cases in an IP component testbench.
The modular organization of scenario models enables reuse from the IP component to the SoC level and across projects, derivatives and new SoC platforms. For example, an IP driver scenario model contains no system-specific information and can be used with any SoC that incorporates the IP component.
TrekSoC Test Visualization
TrekSoC provides industry-leading visualization of the multi-threaded, multi-processor C test cases that it generates. These test cases are far more complex than could be written manually, so this visualization is essential for debug when a test case uncovers an error in the SoC design.
The modular graph-based structure of scenario models makes it possible to visualize the possible paths and the constraints applied to those paths. TrekSoC provides reachability analysis on the scenario model that highlights unreachable test cases. These visualization capabilities make it convenient to review the SoC verification model for completeness.
TrekSoC tracks the paths through the model that have been exercised, to provide a clear picture of scenario elements still to be covered. The achieved coverage can be visualized as a hot-spot graph and analyzed to ensure that cross-coverage cases of interest have been evaluated. This scenario-level coverage is complementary to traditional coverage methods and provides a high quality metric of real functional, or specification, coverage.
TrekSoC is interfaced to standard debug environments. In particular the integration with the well-known Synopsys Verdi environment is particularly powerful with cross probing, breakpoints and other capabilities. TrekSoC’s display may be invoked from Verdi with a special button. TrekSoC integrates with Verdi’s hardware/software displays and Verdi Planner coverage tracking to providing a complete analysis solution.
TrekSoC in Real Environments
TrekSoC is in use today at many leading electronics companies. Its particular strength at the SoC level is stress testing complex environments that are often seen in processor, multi-media and communications designs. The companies using these tools have seen their testbench creation time shrink from months to days, and the quality of those tests improve by an order of magnitude.