TrekUVM™: Eliminating UVM Overhead
Multi-threaded sequences automatically synthesized from easily authored, abstract scenario graphs
Scoreboards and coverage models synthesized for self-verifying, automated coverage closure
Layers into existing UVM testbenches & VIP; tight verification environment integration (e.g., Verdi)
The Universal Verification Methodology (UVM), leveraging SystemVerilog, is now the predominant method used to create test benches for IP blocks running in simulation. While this has advantages in terms of standardizing testbench architectures and reusing Verification Intellectual Property (VIP) blocks, UVM does have certain drawbacks.
The generation of nested sequences that provide synchronized testing across all of the ports on a design can be cumbersome and error prone, and this is further exacerbated if these sequences must be leveraged at the SoC level with software C-tests. In addition, an authoring overhead is implied for certain structures, such as scoreboards and coverage models, which can prove tedious to build and often must be recreated for new projects. Finally, ensuring the sequences are correct and reviewing them with an entire team can be time consuming.
TrekUVM: Simplifying Testbench Creation
TrekUVM supports a natural thought process about chip verification, helping you “mind map” how the design should work and what the verification flow should be. It helps you create scenario models that define your verification space in a textual or an intuitive graphical form, allowing you to deliver a modular, extensible, and scalable solution for the functional verification of large, complex chips.
From your scenario models, TrekUVM generates test cases using UVM transactions and connects to the input and outputs of your chip via your existing UVM verification components (UVCs) without requiring a complete testbench. Specifically, you do not need to provide a virtual sequencer, a scoreboard, or a chip-level coverage model. The test cases generated by TrekUVM include input stimulus, results checking, and coverage. This provides completely automated controllability and monitoring of your design.
TrekUVM in a Typical Verification Flow
TrekUVM works in precisely the same way for IP blocks, clusters of IP blocks, or complete chips. In all cases the existing UVM testbench and UVCs are leveraged to connect to the design. Lower-level graphs can be composed together to form scenario models at the next level in the design hierarchy. This level of verification reuse is not possible with other testbench elements such as virtual sequencers.
- Modular, extensible, and scalable solution for UVM verification
- Flexible, incremental deployment with high return on investment (ROI)
- Visualization and coverage analysis of verification scenarios
- Reusable verification modules
TrekUVM Scenario Models
TrekUVM takes as input a hierarchy of graph-based scenario models that are based on the Accellera Portable Stimulus Standard. Scenario models are developed using a simple paradigm of graphs and graph constraints. There are only a small number of constructs to learn. Scenario models “begin with the end in mind” by starting with the possible outcomes. The TrekUVM test case generator walks the graph, randomizing both selection points and data values as it generates the test cases for the chip.
At test generation time, as opposed to test run time, TrekUVM makes constrained-random decisions about services in order to stress chip interactions. This strategy yields individual test cases that are efficient, repeatable, and simple to debug while allowing sophisticated decisions to be made for each decision point in the graph. This process may be coverage-driven through the TrekUVM automated coverage closure mechanism.
TrekUVM Visual Coverage
The modular graph-based structure of scenario models makes it possible to visualize the possible paths and the constraints applied to those paths. TrekUVM provides reachability analysis on the scenario model that highlights unreachable test cases. These visualization capabilities make it convenient to review the chip verification model for completeness.
TrekUVM tracks the paths through the model that have been exercised. The achieved coverage can be visualized as a hot-spot graph and analyzed to ensure that cross-coverage cases of interest have been exercised. This scenario-level coverage is complementary to traditional coverage metrics.
Achieving full functional coverage is simplified through the TrekUVM automated coverage closure mode. Using this option, tests will be generated that guarantee all available paths through the graph model will be exercised. Furthermore, the coverage results may be exported back into the SystemVerilog models for complete recording.
The modular organization of scenario models enables reuse from the IP component to the full-chip level and across projects, derivatives, and new platforms. For example, an IP driver scenario model contains no system-specific information and can be used with any UVM that incorporates the IP component.
TrekUVM Test Case Visualization
TrekUVM provides industry-leading visualization of the multi-threaded test cases that it generates. The scenario models show where parallelism is possible in the design, and TrekUVM will exploit this in order to stress the chip as much as possible. In this example, there might be multiple concurrent transactions active within the crossbar as well as multiple transactions executing serially in the queue.
This unique visualization display is generated by TrekUVM to coordinate activity between the UVC testbench, components on the UVM I/O ports, and the overall test case. The display is updated in real time as the simulation progresses.