System-level coverage models can be automatically extracted from a scenario model, offering a wide range of possibilities for coverage metrics at a higher level than traditional code and functional coverage. Because this coverage can be directly correlated to driver and application scenarios, it can extend test generation and coverage beyond simulation into hardware. The same scenario models can generate test cases to run on in-circuit emulators, FGPA prototypes and even the actual silicon to assess the total system coverage achieved across these platforms.
Featured Case Study
Broadcom made use of Breker’s TrekSoC Portable Stimulus Test Synthesizer on one of their latest devices. This case study discusses the verification of power domain activation mixing UVM tests and C code running on a CPU.
Featured White Paper
Test Suite Synthesis holds tremendous promise for semiconductor functional verification, particularly in UVM block-level environments. Today scaling UVM test content for large blocks and sub-systems is problematic. The use of synthesis to solve these issues seems obvious. However, the language learning curve for formats such as PSS is significant. SystemUVM™ is designed to solve this problem by providing a linguistic approach extremely close to UVM/SystemVerilog with the power to easily compose specification models for this process.
The 40-minute video introduces you to SystemUVM, a framework designed to simplify specification model composition for test content synthesis with a UVM/SystemVerilog syntactic and semantic approach familiar to universal verification methodology (UVM) engineers. The video demonstrates how Breker’s SystemUVM UVM-style specification model drives test content synthesis, leveraging artificial intelligence (AI) planning algorithms for deep sequential bug hunting in existing UVM environments.
Find out more in our recent SystemUVM announcement.