Honored for Her Financial Experience, Operations Management and Commitment to Entrepreneurship to Bring Change
SAN JOSE, CALIF. –– May 19, 2022 –– Maheen Hamid, founder, COO and CFO of Breker Verification Systems, the leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments, was named today one of Silicon Valley’s 100 most influential women by Silicon Valley Business Journal.
Hamid will be honored during the Women of Influence Award Ceremony at the San Jose Hilton Signia in San Jose, Calif., Thursday, June 16, along with other recipients selected from the private, public and nonprofit sectors. The women are business owners, executives and entrepreneurs like Hamid and community leaders, all of whom are making a mark in Silicon Valley.
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Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios
/by becbrekAutomated Test Generation Verification IP Elements Focus on Difficult Scenarios for Broad Range of Processor Cores and SoCs
SAN JOSE, CALIF. –– December 13, 2022 –– Breker Verification Systems, the leading provider of advanced test content synthesis solutions, today unveiled the Breker Integrity FASTApps™ Portfolio, a library of automated test generation intellectual property (IP) elements targeting difficult-to-verify processor core and system-on-chip (SoC) scenarios.
The FASTApps provide commercial-grade, high-coverage verification for RISC-V processor cores and the SoC platforms that use them.
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Breker Verification Systems and Codasip Announce Co-operation to Drive Open, Commercial-Grade RISC-V SoC Verification Processes
/by becbrekProven Verification Leaders Collaborate on Open SoC Scenario Validation Standards, Methodologies, and Metrics
SAN FRANCISCO –– July 11, 2022 –– Breker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency, and Codasip, the leading supplier of customizable RISC-V processor IP, today announced an extensive technical collaboration to develop and improve rigorous verification processes for common RISC-V SoC scenarios.
Today’s announcement comes as Breker and Codasip demonstrate their RISC-V SoC verification and processor IP solutions at Design Automation Conference (DAC) in Booth #2528 and #1451, respectively, at Moscone West here.
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Imperas Announces Partnership with Breker to Drive Rigorous Processor to System Level Verification for RISC-V
/by becbrekWith a unified, standards-based approach to verification and Verification IP reusability, mutual customers can seamlessly transition between RISC-V processor and system level DV
Oxford, United Kingdom, July 7th, 2022 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced a partnership with Breker Verification Systems, a leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments.
With a combined approach to standards-based verification, development teams will be able to efficiently transition from RISC-V processor functional design verification (DV) right through to system level and SoC integration testing, including automated cache coherency validation.
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Breker Verification Systems Joins RISC-V International as a Strategic Member to Drive Cache Coherency and SoC Integration Verification Methodologies
/by becbrekLeveraging De-Facto Standard Cache Coherency and Integration Test Solutions for Rigorous, Commercial Grade RISC-V Verification
SAN JOSE, CALIF. –– June 30, 2022 –– Breker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency and other SoC integration Verification Intellectual Property (VIP) in the “TrekApps” family, today joined RISC-V International (RVI) as a strategic member.
Breker will offer its expertise in SoC verification solutions to the RVI working groups.
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Breker Verification Systems’ Maheen Hamid Named to 100 Most Influential Women in Silicon Valley List by Silicon Valley Business Journal
/by becbrekHonored for Her Financial Experience, Operations Management and Commitment to Entrepreneurship to Bring Change
SAN JOSE, CALIF. –– May 19, 2022 –– Maheen Hamid, founder, COO and CFO of Breker Verification Systems, the leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments, was named today one of Silicon Valley’s 100 most influential women by Silicon Valley Business Journal.
Hamid will be honored during the Women of Influence Award Ceremony at the San Jose Hilton Signia in San Jose, Calif., Thursday, June 16, along with other recipients selected from the private, public and nonprofit sectors. The women are business owners, executives and entrepreneurs like Hamid and community leaders, all of whom are making a mark in Silicon Valley.
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Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering
/by becbrekEnhances Bug Hunting by Simplifying Specification Model Composition for Test Content Synthesis in Existing UVM Environments
SAN JOSE, CALIF. –– February 28, 2022 –– Breker Verification Systems used the opening of DVCon U.S. today to unveil SystemUVM™, a framework designed to simplify specification model composition for test content synthesis with a UVM/SystemVerilog syntactic and semantic approach familiar to universal verification methodology (UVM) engineers.
Developed in partnership with leading semiconductor companies, Breker’s SystemUVM’s UVM-style specification model drives test content synthesis, leveraging artificial intelligence (AI) planning algorithms for deep sequential bug hunting in existing UVM environments.
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NucleiSys Adopts Breker’s System Coherency TrekApp
/by becbrekAdvantages Include Ease of Use, Fast Setup, Considerable Verification Coverage, Flexible Scaling to Meet Future Verification Needs
SAN JOSE, CALIF. –– January 25, 2022 –– Breker Verification Systems today announced Nuclei System Technology deployed its System Coherency TrekApp to ensure coherency of its configurable low-power and high-performance 32- and 64-bit RISC-V processor intellectual property (IP) designs.
“After an extensive evaluation, we choose Breker’s System Coherency TrekApp to help to ensure our design’s coherency,” remarks JianYing Peng, CEO of Nuclei System Technology. “TrekApp offers ease to use and extremely fast setup and covers broad aspect of verification from simple workload to complex scenarios that includes Dekker and Atomics tests.”
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Security: Making the Unknown, Known
/by Adnan HamidThere is no known way to guarantee that a system is secure. Vulnerabilities exist in hardware, software, and throughout the supply chain. They may exist by accident or by ignorance. They may have been inserted maliciously, or they may utilize some mechanism never before considered part of the attack plane. There is no one method by which all these potential issues can be addressed, and no tool that can find them all.
Security has often been likened to a castle. You build layers of protection and while you expect some to be breached, you make it increasingly difficult to get the ultimate prize. Verification has a role to play in exposing vulnerabilities, but the problem is that entrenched dynamic verification methodologies have difficulties with this. Technologies are needed that can produce testcases which demonstrate a weakness. Formal verification is one that has been successfully used for this.
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Breker Verification Systems Unveils System Coherency Synthesis TrekApp, Building on Its Successful Cache Coherency Test Solution
/by becbrekSystem Coherency Synthesis TrekApp Generates High Coverage Tests to Stress Coherency, Detect Corner Cases for Range of SoC Platforms, Processors
AT DESIGN AUTOMATION CONFERENCE BOOTH #2528
SAN JOSE, CALIF. –– December 6, 2021 –– Breker Verification Systems today unveiled its System Coherency Synthesis TrekApp used to generate thousands of high-coverage tests to stress cross-system coherency for a broad range of SoC platforms and processors.
Based on Breker’s Cache Coherency TrekApp, the System Coherency Synthesis TrekApp uses abstract models of common and novel algorithms to automatically generate coherency test content for complex, multi-agent system platforms based on coverage directives. The TrekApp can be configured for Arm, RISC-V and other processor configurations and broad range of storage and I/O architectures.
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Inside Portable Stimulus — Hardware Software Interface
/by Leigh BradyThis blog series has stuck to what is in the Accellera Portable Stimulus 1.0 standard (PSS), but in this particular blog, we will deviate a bit. We will discuss a capability that did not make it into the first release of the standard, the Hardware Software Interface (HSI). It is a critical capability that now has the full attention of the Accellera Portable Stimulus Working Group (PSWG). Its absence results in extra work for companies that want to adopt Portable Stimulus tools without some form of this functionality.
The problem is easiest to understand by thinking about test portability. By that, we mean the ability to go from a single description of test intent and to execute that test, without modification, on a variety of execution engines. Those execution engines include simulators, running at either the transaction level or register transfer level (RTL), emulators, prototyping solutions, virtual platforms, and real silicon. Now, consider a test that needs to get data into a certain register or memory location or retrieve the contents of that register or memory to ensure that a test operated correctly.
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