The Road to Coverage is Paved with Good Intentions
A Discussion of Intent-based Coverage and its Practical Application on Advanced Verification Scenarios
At the recent Design Automation Conference 2023, Adnan Hamid, Breker’s CTO, participated in a panel that looked at the next generation of verification coverage. This 10-minute video is his presentation at the event, which discusses “Intent-based Coverage,” verification coverage analysis based on the original intention of a design specification. This has proven highly effective in understanding verification quality, particularly for complex scenarios such as coherency and security verification, scenarios that are hard to analyze using traditional techniques. In 10 minutes Adnan provides a discussion of the problem for these scenarios, how intent-based coverage may be generated and analyzed, why it yields better results, and how it may be applied to both coherency and security. For more information, or to discuss this concept more fully with Adnan, please contact us at firstname.lastname@example.org.
RISC-V SoC Coherency: Dealing with Unique RISC-V Coherency Issues
Modern SoCs with multiple master components, complex storage architectures and advanced fabrics require exacting methods to ensure full system coherency. RISC-V presents greater challenges given its instruction flexibility, the emergence of full application processors and the varied range of potential applications. Coherency is a system problem that must be considered during processor and SoC implementations. End-to-end IP scenarios plus cache coherency, paging, interrupt management together with early firmware all adds to the verification problem, for both hardware-only sub-system test and hardware/software validation. The problem requires unique verification solutions. Breker’s test generator, based on the new Portable Stimulus standard, makes use of a broad range of algorithms to torture test the design from multiple angles. For example, leveraging the Dekker algorithm and combining this with stride testing can tease out numerous corner cases that otherwise may be missed. This talk examines the issues of modern RISC-V SoCs, share the methods that may be used to ensure coherency, and demonstrate examples of this process on complex SoCs.
The New Verification Ecosystem that Supports RISC-V Verification for All Adopters
The RISC-V design freedoms have enabled implementers to innovate new and creative solutions. As a design progresses from concept to completion, the flexibility of RISC-V has implications for the hardware functional verification teams. This talk covers the latest developments in the RISC-V verification ecosystem to address new approaches for processor verification. These include: open standards to support universal testbenches and VIP (Verification IP) reuse, coverage libraries and quantitative measures for test infrastructure quality, and novel techniques to verify cache coherency and SoC integration. Based on examples from several popular open-source cores this talk provides guidelines that can help both open-source and commercial projects address the RISC-V functional verification challenge.
SystemUVM™ — Empowering the UVM Engineering Team
The 40-minute video introduces you to SystemUVM, a framework designed to simplify specification model composition for test content synthesis with a UVM/SystemVerilog syntactic and semantic approach familiar to universal verification methodology (UVM) engineers. The video demonstrates how Breker’s SystemUVM UVM-style specification model drives test content synthesis, leveraging artificial intelligence (AI) planning algorithms for deep sequential bug hunting in existing UVM environments.
Find out more in our recent SystemUVM announcement.
SoC Verification and the Synthesizable VerificationOS™ Workshop
The 45-minute workshop commences with an interview with Intel Principal Engineer Mike Chin where he describes the SoC verification challenges he experiences and considers the concept of a Synthesizable VerificationOS. Adnan Hamid CEO/CTO at Breker then takes the audience through an explanation of how these challenges may be addressed based on Breker’s work with many verification teams.
Find out more about the Synthesizable VerificationOS in our recent product announcement.
Automated Scalable RISC-V Cache Coherency Verification
As the RISC-V ISA is leveraged in more complex extended processors, maintaining cache coherency is becoming a significant factor. Verifying coherency across an SoC with a high degree of coverage is complex and time consuming. Working with RISC-V processor providers, including SiFive, Breker has developed a scalable solution that may be reapplied to different RISC-V processor configurations and runs common cache coherency test techniques across a broad range of cases. Unique integration verification issues that occur due to the open nature of the RISC-V ISA, its extensibility, and some of the applications in which it is being applied have come to light. This presentation shares various approaches to cache coherency verification, how they may be adapted to unique RISC-V issues, and how this may be encapsulated for reusability across different RISC-V applications.
Automating Security Verification Using Test Suite Synthesis and Portable Stimulus
This three-part, 40-minute on-demand video series discusses a solution developed by a leading semiconductor company using the Portable Stimulus Standard (PSS) to drive a Test Suite Synthesis tool equipped with AI Planning Algorithm technology. This semi-formal approach leverages similar ideas to formal verification but can be applied to large systems using simulation or emulation. The method examines the entire design search space for illegal access opportunities, enabling a thorough, high-coverage analysis of all possible vulnerabilities.
Dave Kelf Discusses Test Suite Synthesis
Recorded in April 2020, Breker CMO Dave Kelf discusses Breker’s new Test Suite Synthesis video and white paper and the impact of the shelter-at-home order on the EDA community and business.
Coverage Driven Verification with Breker’s Test Suite Synthesis.
This 3 minute video provides an overview and a short demonstration of Breker’s Test Suite Synthesis technology for Coverage Driven Verification.
The solution is in use today and multiple large semiconductor companies. It provides a powerful method to synthesize high-coverage test content for large scale electronic semiconductor and system verification projects. Working with both UVM block based environments and System-on-Chip (SoC) Software Driven environments, it accelerates the production of test content by 5X while increasing coverage dramatically.
Eliminating Hybrid Verification Barriers Through Test Suite Synthesis
Breker Technical Specialist Aileen Honess discusses Test Suite Synthesis, where verification scenario intent is described using the new Portable Stimulus Standard and then synthesized to the respective process implementation. During the webinar you will see a demonstration of the practical application of test suite synthesis on real designs as they progress from architecture to block to SoC, leveraging hybrid verification techniques.
On-demand webinar recorded August 13, 2019
Portable Test and Stimulus: The Next Level of Verification Productivity is Here
Breker CEO Adnan Hamid co-presents this in-depth tutorial on using the Accellera Portable Stimulus Standard to enable reuse of verification intent throughout the product development process.
Recorded at: DVCon 2018
Dave Kelf Discusses the Portable Stimulus Standard
Recorded at DVCon US 2018, Breker CMO Dave Kelf provides an update on the PSS standard, how Breker is using it in various products, and up and coming capabilities for the products.
Cache Coherency Verification with Vertical and Horizontal Portable Stimulus
Recorded at: DVClub Europe Conference
Date: April 20, 2015
Presenter: Adnan Hamid, Breker Verification Systems