RISC-V MMU Verification of Virtualization and Hypervisor Operation for CPU and SoC Platforms

The advent of RISC-V has presented verification teams with many new verification challenges. Complex interactions at the system level that must be considered when developing a RISC-V core include uncommon scenarios for block-level verification teams. As we move towards more system-level verification and RISC-V Application Processors in general, these types of scenarios will become commonplace. As such, RISC-V verification provides, among many other things, an interesting learning vehicle for general verification challenges to come.

This video discusses a specific complex, yet commonplace, verification challenge for any team working on a complex RISC-V core. We consider the verification of a Memory Management Unit (MMU) that includes virtualization and hypervisor operation. These scenarios need to consider both Single- and Multi-core devices along with an Input Output Memory Management Unit (IOMMU) and uncore IP interaction. The video contains valuable information for any engineer or manager involved with the design of a RISC-V core or using a RISC-V core on their SoC.