Breker’s popular Cache Coherency TrekApp 1.0, as used by most of the leading semiconductor companies worldwide, has found 100s of bugs over many complex SoCs. However, as the complexity of modern SoCs continue to increase, so does the requirement for system level coherency that includes fabric and I/O as well as advanced memory architectures. Breker’s next generation System Coherency technology, leveraging Test Suite Synthesis, has been designed to address these emerging challenges far more effectively than zero abstraction templating and similar schemes.
The Breker System Coherency TrekApp works with Breker’s Test Suite Synthesis technology to generate a broad range of coherency tests based on multiple verification algorithms. It may be easily configured to operate on all memory and fabric architectures across multicore platforms leveraging many types and numbers of processors and multiple coherent agents.
The TrekApp can generate both C code and transactions for System testbenches, or UVM sequences for cache unit and sub-system simulation. It will operate on virtual prototype, simulation, emulation, FPGA prototyping or even actual silicon platforms, and enable full debug and profiling of the device under test on those platforms. Coverage requirements may be entered pre-test generation to provide as comprehensive a test as the execution medium (e.g., simulation, emulation, etc.) will allow.