System Coherency TrekApp

Benefits

Generate 1000s of high-coverage tests to stress coherency and auto-track complex corner cases

Easily configure scenarios for a broad range of SoC platforms & processors with no learning curve

Directly observe multi-threaded cache behavior and easily debug and profile system behavior

Elevating Cache Coherency

Breker’s popular Cache Coherency TrekApp 1.0, as used by most of the leading semiconductor companies worldwide, has found 100s of bugs over many complex SoCs. However, as the complexity of modern SoCs continue to increase, so does the requirement for system level coherency that includes fabric and I/O as well as advanced memory architectures. Breker’s next generation System Coherency technology, leveraging Test Suite Synthesis, has been designed to address these emerging challenges far more effectively than zero abstraction templating and similar schemes.

The Breker System Coherency TrekApp works with Breker’s Test Suite Synthesis technology to generate a broad range of coherency tests based on multiple verification algorithms. It may be easily configured to operate on all memory and fabric architectures across multicore platforms leveraging many types and numbers of processors and multiple coherent agents.

The TrekApp can generate both C code and transactions for System testbenches, or UVM sequences for cache unit and sub-system simulation. It will operate on virtual prototype, simulation, emulation, FPGA prototyping or even actual silicon platforms, and enable full debug and profiling of the device under test on those platforms. Coverage requirements may be entered pre-test generation to provide as comprehensive a test as the execution medium (e.g., simulation, emulation, etc.) will allow.

Modular SoC Verification Solutions for ARM, RISC-V and Other Processor SoCs

The System Coherency TrekApp contains the ARMv8 and ARMv9 instruction sets, as well as the RISC-V Instruction Set Architecture (ISA), including additional custom instructions. This allows it to be easily configured to drive ARM and RISC-V SoCs and sub-systems. In addition, the TrekApp may be easily configured to add instruction sets for other processors.

The TrekApp part of the Breker TrekApp library designed to be incorporated together to form verification scenario platforms for specific purposes. For example, the System Coherency TrekApp can be combined with the RISC-V Integration TrekApp, Security TrekApp, the Power Domain Management TrekApp and custom tests to provide a comprehensive scenario test platform for a new RISC-V processor SoC, ensuring the correct operation of the SoC and the processor within.

System Coherency Capabilities

The System Coherency TrekApp generates tests based on a range of typical and novel algorithms. The verification metrics covered by the TrekApp include:

Cache State Transitions
Cache Line Sharing Cases
Snoop / Probe Sources
Load/Store Operation Size
Load/Store Sources
False Sharing Cases
Crossing Cache Line Boundaries
Capacity Eviction Cases
Address Stride Patterns
Memory Workloads
Multiple Memory Regions
Concurrent Scenarios

In addition, the TrekApp also includes the following, more general processor integration scenarios:

All ARM/RISC-V load/store instructions
Memory Barriers / Ordering
Randomized Interrupts
Randomized Exception Level Switching
Randomized WFE sleep / wakeup
Page Table Randomization (TBA Q1’22)

The TrekApp makes use of a variety of known and proprietary algorithms to accomplish the above metrics, including the Dekker Algorithm, Moesi State Analysis and many others.

NucleiSys Adopts Breker’s System Coherency TrekApp

“After an extensive evaluation, we choose Breker’s System Coherency TrekApp to help to ensure our design’s coherency. TrekApp offers ease to use and extremely fast setup and covers broad aspect of verification from simple workload to complex scenarios that includes Dekker and Atomics tests. Its flexible scaling will scale with us as we go from verifying the coherency of a few CPUs to hundreds of CPUs, matching our needs now and for our future RISC-V solution offerings.”

— JianYing Peng, CEO, Nuclei System Technology

Read the press release >

Configurable, Extendable TrekApps

Configurable, extendable Breker TrekApps

All of the Breker TrekApps allow for universal configuration and extensibility to suit a variety of specialized test scenarios and applications. The System Coherency TrekApp can be easily configured to drive a variety of processor instruction sets, including custom instructions, without changing test scenarios or using specialized languages. Custom test algorithms may also be added, and these will be amalgamated into the test generation process, multiplying the existing tests with the new.

Article: Breker Attacks System Coherency Verification >

Cache Coherency Results

Breker’s Test Suite Synthesis has been shown to produce dramatic improvements in test composition time and coverage over and above basic test generators, including templating schemes. System coherency is a notoriously complex and error prone task which requires considerable expertise and time to accomplish. The System Coherency TrekApp can be set up in a few days and will immediately generate high quality tests with minimal effort. The TrekApp will create test traffic orders of magnitude test density, creating a high coverage execution and exercising hard to predict corner cases.

System Coherency TrekApp

Benefits

Elevating Cache Coherency

Modular SoC Verification Solutions for ARM, RISC-V and Other Processor SoCs

System Coherency Capabilities

NucleiSys Adopts Breker’s System Coherency TrekApp

Configurable, Extendable TrekApps

Cache Coherency Results

Products

TrekApps

Scenario Modeling

Contact Breker