Test Suite Synthesis
Eliminating Hybrid Verification Barriers Through Test Suite Synthesis
This webinar discusses Test Suite Synthesis, where verification scenario intent is described using the new PSS and then synthesized to the respective process implementation. The white box intent description can be used to accelerate UVM block verification, Software Driven Verification (SDV) for SoCs, and prototyping and post-silicon validation, increasing quality while reducing schedules. In addition, this same test description can be used across all these processes, providing a continuous, back and forth flow across the entire verification process. During the webinar you will see a demonstration of the practical application of test suite synthesis on real designs as they progress from architecture to block to SoC, leveraging hybrid verification techniques.
The main portion of the webinar is presented by Aileen Honess. Aileen has more than 20 years of experience teaching, mentoring, and leading hardware verification projects across a variety of disciplines, companies, and continents. She is an expert in UVM and has recently been assisting those who are modernizing their verification methodology by adopting portable stimulus and portable specifications. After a long career at Synopsys as a lead application specialist in verification, she has assumed the role of Technical Specialist at Breker Verification Systems. She holds a BS in Electrical Engineering from UCLA.
Sign up for this On-demand Webinar
Please fill out the following form to view the webinar.