Functional Intent Specification with Portable Stimulus
Breker Scenario Modeling Benefits
Highly descriptive and easy to understand modeling approach that makes use of GRAPHS, a well-known method to detail complex functionality in a comprehendible fashion.
When used with Breker test synthesis, enables PORTABLE scenarios for UVM sequence generation and C-based SoC tests across simulation, hardware verification and actual silicon.
Modular in fashion allowing smaller, UVM block tests to be easily SHARED with SoC teams for incorporation into larger tests, enabling seamless reuse and eliminating authoring redundancy.
Modern semiconductor verification processes are characterized by complex test methodologies, disconnected verification technologies, and a lack of predictability as to process completion. All of these factors lead to wasted resources, schedule slips and a question as to whether final products have truly met their original specifications.
Verification techniques have evolved dramatically over the last twenty years. Even with this continuous introduction of new solutions, techniques and expertize, verification still accounts for approximately 70% of total Integrated Circuit (IC) development time and resources. Most devices require at least one expensive re-spin to fix bugs, and many need two or more. 70% of designs are produced behind schedule, often due to verification problems. (Source: Wilson Research 2016).
Realizing the Executable Intent Specification
For many years, the holy grail of verification was the notion of an executable specification, written in a simple, comprehendible manner to drive the entire verification process and provide functional checks and clear, predictable coverage metrics. Such a methodology would allow engineers to focus on design functionality and pushing the development process to rapid completion.
Although great strides have been made, we are still a long way from this goal. Testbenches (consisting of stimulus, checks and coverage models) have become harder to create than ever, with complicated standards, such as UVM, often getting in the way as much as helping.
Engineering full system tests that synchronize SoC elements, including hardware and software, is a massively complex proposition. Different parts of the verification process require the rewriting of tests as engineers move from block to SoC testing and simulation to emulation. The idea of sharing and reusing tests is still limited to specific code based on standard functional protocols. These represent barriers to productive verification.
What is required is a single, simple specification format that eliminates the overbearing complexity of block UVM and SoC HW/SW test sets, while enabling test portability between verification process elements and reuse across many projects. Breker is the first company to provide such a solution, now in use at many leading semiconductor companies. This is also the driver behind the Accellera Portable Stimulus Standard (PSS), of which Breker is a leading contributor.
The Accellera Portable Stimulus Standard (PSS) and the native C++ modeling approach leveraged by Breker both provide an abstract method to model operational scenarios of a device that may be synthesized into verification tests for different phases of the verification process.
The Accellera Portable Stimulus Standard
Breker is a founding member of the Accellera Portable Stimulus Working Group and has donated a considerable amount of technology to this effort. Breker fully supports the Accellera PSS DSL and C++ based formats. Functionally PSS is a subset of the procedural native C++ modeling method that may also be used with the Breker tools.
Accellera’s PSS committee was formed to drive a common standard for modeling stimulus that could be ported between simulation, emulation and fabricated silicon. This stimulus methodology could drive block level simulation as well as embedded software tests for SoC designs. Two syntactically equivalent formats have been proposed, one with a C++ base and the other, a Domain Specific Language, or DSL, unique to this standard. The 1.0 version of this standard is likely to be released during 2018.
Modeling in Native C++
In addition to fully supporting the Accellera PSS DSL and C++ standard, Breker has developed a native C++ solution solution that, together with its functional test synthesis technology, provides an answer to the above verification issues. While the Accellera PSS standard is largely declarative in nature to allow its use with multiple tools, the native C++ solution builds on top of this with a full procedural capability, allowing for extended test creation that leverages the full power of the Breker Trek functional synthesis technology.
Breker has leveraged native C++ to provide a familiar modeling mechanism with a minimal learning curve and easy application. A class library and a small number of additional features have been added which enables an easy modeling approach leveraging classic graph-based techniques.